A semiconductor device includes a first semiconductor die, a second semiconductor die and a plurality of supporting structures. The first semiconductor die includes a plurality of first bumps disposed adjacent to a first active surface thereof. The second semiconductor die includes a plurality of second bumps disposed adjacent to a second active surface thereof. The second bumps are bonded to the first bumps. The supporting structures are disposed between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die. The supporting structures are electrically isolated and are disposed adjacent to a peripheral region of the second active surface of the second semiconductor die.

An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.

An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.

Systems and techniques that facilitate uniform qubit chip gaps via injection-molded solder pillars are provided. In various embodiments, a device can comprise one or more injection-molded solder interconnects. In various aspects, the one or more injection-molded solder interconnects can couple at least one qubit chip to an interposer chip. In various embodiments, the device can further comprise one or more injection-molded solder pillars. In various instances, the one or more injection-molded solder pillars can be between the at least one quit chip and the interposer chip. In various cases, the one or more injection-molded solder pillars can be in parallel with the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can facilitate and/or maintain a uniform gap between the at least one qubit chip and the interposer chip. In various embodiments, a melting point of the one or more injection-molded solder pillars can be higher than a melting point of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be superconductors. In various embodiments, a yield strength of the one or more injection-molded solder pillars can be between 3,000 pounds per square inch and 15,000 pounds per square inch, which can be higher than a yield strength of the one or more injection-molded solder interconnects. In various embodiments, the one or more injection-molded solder pillars can be binary tin alloys, tertiary tin alloys, and/or quaternary tin alloys.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.

A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Devices and methods related to packaging of radio-frequency (RF) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit and mounted on a surface of the ceramic substrate. The packaged electronic device can further include a conformal conductive coating implemented over the die to provide shielding functionality. The packaged electronic device can further include an electrical connection between the conformal conductive coating and the conductive layer.

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.