An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

A semiconductor package may include: a first semiconductor chip; a second semiconductor chip disposed over the first semiconductor chip; and a bump structure interposed between the first semiconductor chip and the second semiconductor chip to connect the first semiconductor chip and the second semiconductor chip, wherein the bump structure includes a core portion and a shell portion, the shell portion surrounding all side ails of the core portion, and wherein the shell portion has a higher melting point than the core portion.

A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.

A clock circuit constructed in a processor integrated circuit includes a phase lock loop PLL, a clock tree, and a clock grid. The clock tree includes a plurality of clock buffers in a layered structure, The clock tree is configured to receive a first clock signal clk_1 that is output by the phase lock loop PLL, and to output a second clock signal clk_2. A plurality of child node circuits (400) are disposed on some nodes of the clock grid, and are configured to generate a third clock signal clk_3 based on the second clock signal clk_2. The clock grid (330) and the clock tree (320) are distributed on multiple dies in a three-dimensional structure of the processor integrated circuit.

Provided is a semiconductor package, including a lower semiconductor chip, a plurality of semiconductor chips that are disposed on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip, a plurality of nonconductive layers disposed between the plurality of semiconductor chips, a nonconductive pattern that extends from the nonconductive layers and is disposed on lateral surfaces of at least one of the plurality of semiconductor chips, a first mold layer disposed a top surface of the nonconductive pattern, and a second mold layer disposed a lateral surface of the nonconductive pattern and a lateral surface of the first mold layer, wherein the nonconductive pattern and the first mold layer are disposed between the second mold layer and lateral surfaces of the plurality of semiconductor chips.

A semiconductor package includes a first base plate, first semiconductor structure, second base plate and filling layer. The first base plate has a first surface including first and second signal transmission regions. The first semiconductor structure located on the first surface is electrically connected to the first signal transmission region. The second base plate located on the first base plate includes a base and a first interconnection surface. The first interconnection surface is away from the first surface. The first interconnection surface has first and second interconnection regions communicated with each other. The first interconnection region is electrically connected to the second signal transmission region. The filling layer seals the first semiconductor structure, second base plate and first surface. The first interconnection region is not sealed, and the second interconnection region is. There is a preset height between a top surface of the filling layer and the first interconnection region.