Semiconductor devices may include a die including a semiconductor material. The die may include a first active surface including first integrated circuitry on a first side of the die and a second active surface including second integrated circuitry on a second, opposite side of the die. In some embodiments, the die may include two die portions: a first die portion including the first active surface and a second die portion including the second active surface. The first die portion and the second die portion may be joined together with the first active surface facing away from the second active surface.

A chip package structure includes at least one semiconductor die attached to a redistribution structure, a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding the solder material portions, a molding compound laterally surrounding at least one semiconductor die, and a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and including at least one cut region. The second underfill material portion includes a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region.

Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises connection terminals between a first die and a second die. The first die has signal and peripheral regions and includes first vias on the peripheral region. The second die is on the first die and has second vias on positions that correspond to the first vias. The connection terminals connect the second vias to the first vias. The peripheral region includes first regions adjacent to corners of the first die and second regions adjacent to lateral surfaces of the first die. The connection terminals include first connection terminals on the first regions and second connection terminals on the second regions. A sum of areas of the first connection terminals per unit area on the first regions is greater than that of areas of the second connection terminals per unit area on the second regions.

An integrated circuit device includes: a substrate having an active surface, an inactive surface, a first region and a second region; a device structure on the active surface, and including individual devices disposed in the first region and a target through-region disposed in the second region; a multilayer wiring structure including wiring layers, wherein at least one wiring layer among the wiring layers has a landing pad overlapping the target through-region; and a through-via structure connected to the landing pad by penetrating through the second region and the target through-region, wherein the target through-region includes first insulating material patterns and dummy device patterns, wherein the first insulating material patterns each have a first area, wherein the dummy device patterns are on the active surface and each have a second area smaller than the first area, and wherein the first insulating material patterns are alternatively arranged with the dummy device patterns.

A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.

Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

A semiconductor device includes: a semiconductor substrate having opposing first side and second sides; an active region and an isolation region on the first side; a circuit device on the active region; a front side interconnection structure on the first side and including front side interconnection layers disposed on different levels; first and second back side interconnection structures below the second side; a buried structure having a portion disposed in the isolation region and including a conductive line; a first through-electrode structure including a first through-electrode contacting the conductive line and penetrating the semiconductor substrate between the conductive line and the first back side interconnection structure; and a second through-electrode structure including a second through-electrode penetrating the semiconductor substrate between a first front side interconnection layer and the second back side interconnection structure. The first front side interconnection layer is on a level higher than that of the conductive line.