A display device made of a TFT substrate and a driver IC is configured to eliminate bad connection between them. On the driver IC connected to the TFT substrate, a first principal surface has first bumps formed along a first side having a first edge and second bumps formed along a second side opposite to the first side and having a second edge. The TFT substrate has first terminals and second terminals connected to the first and the second bumps, respectively. On a cross section taken perpendicularly to the first and the second sides, the first principal surface has a first area between the first and the second bumps and a second area between the second bumps and the second edge. The first and the second areas are bent toward the TFT substrate.

A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface through which light is emitted. Portions of the p-type layer and active layer are etched away to expose the n-type layer. The surface of the LED is patterned with a photoresist, and copper is plated over the exposed surfaces to form p and n electrodes electrically contacting their respective semiconductor layers. There is a gap between the n and p electrodes. To provide mechanical support of the semiconductor layers between the gap, a dielectric layer is formed in the gap followed by filling the gap with a metal. The metal is patterned to form stud bumps that substantially cover the bottom surface of the LED die, but do not short the electrodes. The substantially uniform coverage supports the semiconductor layer during subsequent process steps.

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.

An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

Embodiments of the present disclosure are directed to a microfluidic delivery system that includes a microfluidic semiconductor die coupled to a flexible interconnect substrate to form an assembly. At least one embodiment is directed to a semiconductor die having an active surface that includes a layout that has electrically active bond pads along one side of the active surface of the die. A second side of the active surface of the die includes one or more mechanical pads.

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.

A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.

Three-dimensional (3D) semiconductor memory structures and methods of forming 3D semiconductor memory structures are provided. The 3D semiconductor memory structure includes a chip comprising a memory and Through-Silicon Vias (TSVs). The 3D semiconductor memory structure further includes a hardware accelerator arranged on and coupled face-to-face to the above chip. The 3D semiconductor memory structure also includes a substrate arranged under the under the (3D) semiconductor memory structure and the hardware accelerator and attached to the TSVs and external inputs and outputs of the memory chip and the hardware accelerator.

Embodiments disclosed herein include multi-die electronic packages. In an embodiment, an electronic package comprises a package substrate and a first die electrically coupled to the package substrate. In an embodiment, an array of die stacks are electrically coupled to the first die. In an embodiment the array of die stacks are between the first die and the package substrate. In an embodiment, individual ones of the die stacks comprise a plurality of second dies arranged in a vertical stack.