Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/18
High density interconnect [HDI] connectors; Manufacturing methods related thereto
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H01L2224/23
Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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H01L2224/24
of an individual high density interconnect connector
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H01L2224/24151
Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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H01L2224/24153
the body and the item being arranged next to each other, e.g. on a common substrate
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H01L2224/24153

SEMICONDUCTOR PACKAGE
20250349761 · 2025-11-13 · ·

A semiconductor package includes a semiconductor chip comprising an active surface and an inactive surface facing each other. At least one antenna module is arranged adjacent to the semiconductor chip. The at least one antenna module comprises a main antenna and a sub-antenna. A redistribution structure is disposed on the semiconductor chip and the at least one antenna module. The redistribution structure electrically connects the active surface of the semiconductor chip to the at least one antenna module. A molding member surrounds the semiconductor chip and the at least one antenna module. The inactive surface of the semiconductor chip and the main antenna are exposed from the molding member, and the sub-antenna is covered by the molding member.