A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n.sup.+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n.sup.+-type semiconductor region NR for a source.

A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.

A power semiconductor device includes an insulating substrate, a semiconductor element, a case, and a wiring member. The case forms a container body having a bottom surface defined by a surface of the insulating substrate, to which said semiconductor element is bonded. The wiring member has a bonding portion positioned above an upper surface electrode of the semiconductor element. The bonding portion of the wiring member is provided with a projection portion projecting toward the upper surface electrode of the semiconductor element and bonded to the upper surface electrode with a solder, and a through hole passing through the bonding portion in a thickness direction through the projection portion.

A semiconductor module of the present invention includes: a semiconductor element having a first main surface and a second main surface facing the first main surface, the semiconductor element including a front surface electrode and a back surface electrode on the first main surface and the second main surface, respectively; a metal plate electrically connected to the back surface electrode of the semiconductor element through a sintered bonding material including metal nanoparticles; and a plate-shaped conductor electrically connected to the front surface electrode of the semiconductor element through the sintered bonding material including the metal nanoparticles. The metal plate and the conductor include grooves communicating between a bonding region bonded to the semiconductor element and the outside of the bonding region.

In a power semiconductor device, an IGBT has a collector electrode bonded to a metal plate by a bonding material. A diode has a cathode electrode bonded to the metal plate by the bonding material. An interconnection member is bonded to an emitter electrode of the IGBT by a bonding material. The bonding material includes a bonding material and a bonding material. The bonding material is interposed between the IGBT and the interconnection member. The bonding material fills a through hole formed in the interconnection member. The bonding material reaches the bonding material and is therefore connected to the bonding material.

A power module providing an improved manufacture yield and having an ensured stable joint strength and accordingly improved reliability is provided. The power module includes: a base portion having one surface on which an electrode portion is formed; a conductor portion disposed to face the one surface of the base portion on which the electrode portion is formed, for making electrical connection with the outside; and an interconnect portion connected to the electrode portion formed on the one surface of the base portion and to the surface of the conductor portion facing the one surface of the base portion for electrically connecting the electrode portion to the conductor portion.

An electronic device includes a package structure, conductive leads, first and second semiconductor dies, and a metal clip, The package structure has opposite longitudinal ends, opposite lateral sides, a middle portion midway between the longitudinal ends, a first portion that extends between the middle portion and one longitudinal end, and a second portion that extends between the middle portion and the other longitudinal end. The metal clip extends in the package structure from the first portion to the second portion through the middle portion and electrically couples the first electronic component of the first semiconductor die to the second electronic component of the second semiconductor die.

A semiconductor module, including: a stacked substrate including a plurality of circuit boards formed on an upper surface of an insulating plate; a semiconductor element formed on an upper surface of one of the plurality of circuit boards; and a metal wiring board formed on an upper surface of the semiconductor element. The metal wiring board has a bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The plate-shaped portion has a roughened region in which a plurality of recessed portions are formed on the upper surface of the plate-shaped portion. The plurality of recessed portions include a plurality of first recessed portions that each has a peeling suppressing portion protruding inward to thereby narrow a width of each first recessed portion.

An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between the first and second substrates such to electrically couple the first and second substrate; a constraint layer disposed over the first and second substrates such that a cavity is formed between the constraint layer and the first substrate; and a molding material disposed within the cavity and extending through the constraint layer. The constraint layer has a top surface and an opposing bottom surface and the molding material extends from the top surface to the bottom surface of the constraint layer.

In one embodiment, methods for making semiconductor devices are disclosed.