Patent classifications
H01L2224/37011
Semiconductor module
To provide a semiconductor module that has high reliability of electric connection by a solder and is inexpensive. A joint surface of an electrode jointing portion that is opposed to a surface to be jointed of a gate electrode of a bare-chip FET and a joint surface of a substrate jointing portion that is opposed to a surface to be jointed of another wiring pattern include an outgas releasing mechanism that makes outgas generated from a molten solder during solder jointing of a metal plate connector be released from solders interposed between the joint surfaces and the surfaces to be jointed.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.
POWER MODULE AND POWER CONVERSION APPARATUS
A power module includes: a first metal brazed substrate; a chipset disposed on the first metal brazed substrate, where the chipset includes at least two chips; and a clip, where the clip covers a side, away from the first metal brazed substrate, of the chipset. Each connecting unit is electrically connected to a corresponding chip. Every two adjacent connecting units are connected along a first direction through a body. Each connecting arm is arranged with respect to two adjacent chips in the chipset. The connecting arm is connected to the first metal brazed substrate. A shortest distance between the connecting arm and one of the two adjacent chips is a first shortest distance, a shortest distance between the connecting arm and the other of the two adjacent chips is a second shortest distance. A difference between the first shortest distance and the second shortest distance falls within a preset threshold.
Semiconductor devices and methods of making the same
In one embodiment, methods for making semiconductor devices are disclosed.
SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element that includes a first electrode and a second electrode facing the first electrode in a first direction, a first conductor, and a first fixing member. The first conductor includes a first portion facing the first electrode in the first direction, and a second portion at least partially spaced apart from and facing the first portion in the first direction. The first fixing member is provided between the first electrode and the first portion, and between the first portion and the second portion in the first direction.
SEMICONDUCTOR DEVICE
In a semiconductor device, a multilayer substrate includes an insulating substrate, a first circuit board having a first semiconductor chip disposed thereon, and a second circuit board having a second semiconductor chip disposed thereon. On the multilayer substrate of the semiconductor device, a plate portion of a resin plate including a first positioning portion that regulates the position of each semiconductor chip is sandwiched between a first jumper terminal, which includes a first terminal connected to the first semiconductor chip and a first plate member perpendicular to the first terminal, and a second jumper terminal, which includes a second terminal connected to the second semiconductor chip and a second plate member perpendicular to the second terminal.
SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING A SEMICONDUCTOR MODULE
A semiconductor module, including: a stacked substrate; a semiconductor device mounted on the stacked substrate; a lead frame electrically connected to the semiconductor device; and an encapsulation resin that encapsulates the semiconductor device, the lead frame, and the stacked substrate. The lead frame has a bonding portion bonded to the semiconductor device, the bonding portion having a plurality of recesses provided thereon.
Power substrate assembly with reduced warpage
A substrate assembly may include a power substrate, a chip, a clip, and a trimetal. The power substrate has a first direct copper bonded (DCB) surface connected to a ceramic tile. The chip is soldered onto the first DCB surface. The clip is attached to the power substrate and has a foot at one end and a recessed area at the other, opposite end. The foot is connected to the power substrate. The trimetal has a base, a trapezoid structure, and a clip portion. The base is soldered to the chip. The trapezoid structure is located above the base. The clip portion is located above the trapezoid structure and includes a projecting area. The recessed area of the clip fits into the projecting area of the trimetal.
Wiring structure and semiconductor module
A lead frame structure for connecting a semiconductor chip to a connection target includes a conductive member electrically connecting the semiconductor chip and the connection target. The conductive member includes a first bonding part having a main surface, disposed on one side of the conductive member and being bonded to the semiconductor chip, a second bonding part having a main surface, being disposed on another side of the conductive member that is spaced from the one side in one direction and being bonded to the connection target, and a joining part having a wall section intersecting the main surface of the first bonding part and the main surface of the second bonding part, the wall section joining a portion of the first bonding part to a portion of the second bonding part.
ELECTRICAL CONNECTING MEMBER AND SEMICONDUCTOR DEVICE
An electrical connecting member has a plate shape and is configured for connecting an electrode of a semiconductor element that has the electrode and a wiring pattern. The electrical connecting member includes: a semiconductor connection region that is connected to the electrode of the semiconductor element via a conductive bonding material; a semiconductor non-connection region that is not connected to the electrode of the semiconductor element; and a wiring pattern connection region that is connected to the wiring pattern, wherein a plurality of protrusions are formed in the semiconductor connection region, and a first through hole is formed between two protrusions disposed adjacently to each other out of the plurality of protrusions.