A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.

A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.

A package structure applied to power converters can include: a first die having a first power transistor and a first control and drive circuit; a second die having a second power transistor; a connection device configured to couple the first and second power transistors in series between a high-level pin and a low-level pin of a lead frame of the package structure; and where a common node of the first and second power transistors can be coupled to an output pin of the lead frame through a metal connection structure with a low interconnection resistance.

A package structure applied to power converters can include: a first die having a first power transistor and a first control and drive circuit; a second die having a second power transistor; a connection device configured to couple the first and second power transistors in series between a high-level pin and a low-level pin of a lead frame of the package structure; and where a common node of the first and second power transistors can be coupled to an output pin of the lead frame through a metal connection structure with a low interconnection resistance.

A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process.

A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process.

A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.

A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.