Patent classifications
H01L2224/41052
STACKED CLIP DESIGN FOR GaN HALF BRIDGE IPM
An electronic device includes a substrate having first and second conductive traces, a semiconductor die having a transistor with a first terminal and a second terminal, and first and second metal clips. The first metal clip has a first end portion coupled to the first terminal of the transistor, and a second end portion coupled to the first conductive trace of the substrate. The second metal clip has a first end portion coupled to the second terminal of the transistor and a second end portion coupled to the second conductive trace of the substrate, and a middle portion of the second metal clip is spaced apart from and at least partially overlying a portion of the first metal clip.
METHOD FOR FABRICATING STACK DIE PACKAGE
In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.
Method for fabricating stack die package
In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.
SEMICONDUCTOR PACKAGE HAVING A LEADFRAME WITH A METAL-PLATED BOND AREA
A semiconductor package includes a semiconductor die having a first surface and a second surface opposite the first surface. A die pad is disposed at the first surface of the semiconductor die. A leadframe includes a carrier section on which the semiconductor die is mounted. The semiconductor die is solder-bonded to the carrier section with the second surface facing the carrier section. A metal-plated bond area is provided on the carrier section of the leadframe. A metal of the metal-plated bond area is different from a metal of the leadframe. An electrical conductor is connected to the die pad and bonded to the metal-plated bond area. The metal-plated bond area has a substantially triangular shape.
Connecting strip for discrete and power electronic devices
A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.
CONNECTING STRIP FOR DISCRETE AND POWER ELECTRONIC DEVICES
A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.
Stacked clip design for GaN half bridge IPM
An electronic device includes a substrate having first and second conductive traces, a semiconductor die having a transistor with a first terminal and a second terminal, and first and second metal clips. The first metal clip has a first end portion coupled to the first terminal of the transistor, and a second end portion coupled to the first conductive trace of the substrate. The second metal clip has a first end portion coupled to the second terminal of the transistor and a second end portion coupled to the second conductive trace of the substrate, and a middle portion of the second metal clip is spaced apart from and at least partially overlying a portion of the first metal clip.