Patent classifications
H01L2224/41175
Semiconductor package structure
A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.
Semiconductor device and method for producing semiconductor device
A semiconductor device includes a semiconductor element, leads, and an encapsulation resin covering a portion of each of the leads and the semiconductor element. Each of the leads includes an external connection portion projecting from a side surface of the encapsulation resin. The external connection portion of at least one of the leads has opposite ends in a width-wise direction that extends along the side surface of the encapsulation resin. The external connection portion includes two recesses arranged toward a center in the width-wise direction from the opposite ends. The two recesses extend from a distal surface toward the encapsulation resin. The opposite ends in the width-wise direction define an end connection part. The external connection portion includes a part between the two recesses defining a center connection part.
Multi-Clip Structure for Die Bonding
A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.
Multi-phase power converter with common connections
In some examples, a device comprises at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprises at least two power transistors, an input node on a first side of the respective semiconductor die, a reference node on the first side of the respective semiconductor die, and a switch node on a second side of the respective semiconductor die. The device further comprises a first conductive element electrically connected to the respective input nodes of the at least two semiconductor die. The device further comprises a second conductive element electrically connected to the respective reference nodes of the at least two semiconductor die.
Semiconductor device and method of manufacturing the same
A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.
PACKAGED TRANSISTOR WITH CHANNELED DIE ATTACH MATERIALS AND PROCESS OF IMPLEMENTING THE SAME
A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.
Power semiconductor device and method for manufacturing same
In a power semiconductor device, an IGBT has a collector electrode bonded to a metal plate by a bonding material. A diode has a cathode electrode bonded to the metal plate by the bonding material. An interconnection member is bonded to an emitter electrode of the IGBT by a bonding material. The bonding material includes a bonding material and a bonding material. The bonding material is interposed between the IGBT and the interconnection member. The bonding material fills a through hole formed in the interconnection member. The bonding material reaches the bonding material and is therefore connected to the bonding material.
STACKED CLIP DESIGN FOR GaN HALF BRIDGE IPM
An electronic device includes a substrate having first and second conductive traces, a semiconductor die having a transistor with a first terminal and a second terminal, and first and second metal clips. The first metal clip has a first end portion coupled to the first terminal of the transistor, and a second end portion coupled to the first conductive trace of the substrate. The second metal clip has a first end portion coupled to the second terminal of the transistor and a second end portion coupled to the second conductive trace of the substrate, and a middle portion of the second metal clip is spaced apart from and at least partially overlying a portion of the first metal clip.
Semiconductor device
The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.