A semiconductor module includes a first semiconductor chip having a first top surface on which a first control electrode and a first main electrode are disposed, a second semiconductor chip having a second top surface on which a second control electrode and a second main electrode are disposed, and a plate-shaped wiring member facing, and being electrically connected to, the first and second main electrodes, in which the first semiconductor chip is spaced apart from the second semiconductor chip in a first direction in plan view, the first top surface has a first-peripheral edge in the first direction, the first control electrode is interposed between the first-peripheral edge and the first main electrode, the second top surface has a second-peripheral edge in a second direction opposite to the first direction, and the second control electrode is interposed between the second-peripheral edge and the second main electrode.

An electronic device made from the method of providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, laser bending the shaped metallic interconnects; and transferring the shaped metallic interconnects onto a receiving substrate or device.

A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, and transferring the shaped metallic interconnect to an electrical device. An electronic device made from the method of providing a donor ribbon, wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate, providing a stencil to the metal structures on the donor substrate, applying a laser pulse through the donor substrate to the metal structures, and directing the metal structures to an electronic device.

A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, and transferring the shaped metallic interconnect to an electrical device. An electronic device made from the method of providing a donor ribbon, wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate, providing a stencil to the metal structures on the donor substrate, applying a laser pulse through the donor substrate to the metal structures, and directing the metal structures to an electronic device.

A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, and transferring the shaped metallic interconnect to an electrical device. An electronic device made from the method of providing a donor ribbon, wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate, providing a stencil to the metal structures on the donor substrate, applying a laser pulse through the donor substrate to the metal structures, and directing the metal structures to an electronic device.

A method of forming and transferring shaped metallic interconnects, comprising providing a donor substrate comprising an array of metallic interconnects, using a laser system to prepare the metallic interconnects, forming shaped metallic interconnects, and transferring the shaped metallic interconnect to an electrical device. An electronic device made from the method of providing a donor ribbon, wherein the donor ribbon comprises an array of metal structures and a release layer on a donor substrate, providing a stencil to the metal structures on the donor substrate, applying a laser pulse through the donor substrate to the metal structures, and directing the metal structures to an electronic device.

A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis a and a short axis b of 10 or more and with an area of 15 m.sup.2 or more (fiber texture), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction <100> with an angle difference with respect to the wire longitudinal direction of 15 or less is, by area ratio, 10% to less than 50%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction <100> with an angle difference with respect to the wire longitudinal direction of 15 or less is, by area ratio, 70% or more. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.

Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis a and a short axis b of 10 or more and with an area of 15 m.sup.2 or more (fiber texture), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction <100> with an angle difference with respect to the wire longitudinal direction of 15 or less is, by area ratio, 50% to 90%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction <100> with an angle difference with respect to the wire longitudinal direction of 15 or less is, by area ratio, 50% to 90%. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.

A press pack power semiconductor device can include a housing, a semiconductor, and a locator strip deformed into a ring-like shape to concentrically fit within the housing and concentrically locate at least part of the semiconductor therein. The locator strip can include a first plurality of regions regularly interspersed with a second plurality of regions along a length of the locator strip, and each of the first plurality of regions can have a first cross-sectional area that can be smaller than a second cross-sectional area of each of the second plurality of regions.