A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.

According to one embodiment, a semiconductor device includes a substrate, a chip stack with a plurality of first semiconductor chips, a first wire group, a second wire, and a third wire. The substrate has a first surface with a first pad and a second pad. Each first semiconductor chip has a surface facing away from the first surface with a third pad and a fourth pad. The first wire group includes a plurality of first wires that each electrically connect the first pad to a third pad one of the first semiconductor chips. The second wire electrically connects the second pad to the fourth pad of the first semiconductor chip in the chip stack closest to the substrate. The third wire electrically connects the fourth pads of each of first semiconductor chips.

The present description concerns a device comprising at least one chip in a package, the package comprising a support, having the at least one chip resting thereon, and a protection layer covering the at least one chip, the support comprising a stack of layers made of an insulating material, a transformer being formed in the support by first and second conductive tracks.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.

The present disclosure discloses a trench Insulated Gate Bipolar Transistor (IGBT) packaging structure and a method for manufacturing the trench Insulated Gate Bipolar Transistor packaging structure. The trench IGBT packaging structure includes: a trench IGBT, which includes an emitting electrode metal layer, and a trench gate electrode; a lead frame, which includes a chip placement area and an emitting electrode lead-out end; a first bonding wire connecting the emitting electrode metal layer and an emitting electrode pin. One end of the first bonding wire is connected to a surface, away from the trench gate electrode, of the emitting electrode metal layer to form a strip-shaped first solder joint, the other end is connected to the emitting electrode lead-out end to form a second solder joint, and an extension direction of the first solder joint is perpendicular to an extension direction of the trench of the trench gate electrode.

An electronic device includes: a substrate; a first electronic component that is mounted on a first surface of the substrate; a cap that accommodates the first electronic component between the cap and the substrate; and a mold portion that bonds the cap and the substrate. The cap includes a base portion having a recess that opens to a substrate side and accommodates the first electronic component, and a flange portion that protrudes from an end portion of the base portion on the substrate side to an outer peripheral side and is in contact with the first surface. The mold portion is provided from a second surface side of the substrate to a first surface side while bypassing a side, and bonds the cap and the substrate by molding the flange portion in a portion on the first surface side.

A semiconductor sensor device is assembled using a lead frame having a flag surrounded by lead fingers. A pressure sensor die is mounted on the flag and electrically connected to the leads. Prior to encapsulation, a pre-formed block of gel material is placed over the sensor region on the die. Encapsulation is performed and mold compound covers the pressure sensor die and the bond wires. Mold compound covering the gel block may be removed. Additionally, a trench may be formed around an upper portion of the gel block so that the lateral sides of the gel block are at least partially exposed.

A circuit board and package assembly electrically connecting a die to a circuit board. The circuit board has signal paths terminating in a signal pad located on an insulating layer. The circuit board also includes a ground pad on the insulating layer that has a concave shaped side forming a recess, the with a signal pad at least partially within the recess. A package has package ground pads aligned with the circuit board ground pads and package signal pads aligned with circuit board signal pads. The package ground pads extend through the package to connect to package ground paths, which extend toward the die. The package signal pads extend through the package to connect to package signal paths and the package signal paths extend toward the die, maintaining a consistent distance from the package ground paths. Multiple-tier bond wires connect the package bond locations to the die bond pads.

A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

A method for instillation molding UV epoxy resin includes: the UV epoxy resin preparation step: adding at least two photosensitizers to a single component epoxy resin and uniformly mixing them to obtain the UV epoxy resin, wherein the photosensitizer with the highest content in the UV epoxy resin is a photosensitive curing agent for curing the UV epoxy resin, and the rest photosensitizers are photosensitive viscosity regulating agents for regulating the viscosity of the UV epoxy resin to be suitable for instillation molding; and instillation step: dividing the instillation molding of the UV epoxy resin into N procedures performed in one work station, wherein zero, one or more photosensitive viscosity regulating agents are initiated in each procedure, so that the UV epoxy resin reaches a viscosity suitable for respective instillation procedure and is subsequently instillation molded; curing step: initiating the photosensitive curing agent to finally cure the UV epoxy resin.