A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

A semiconductor package includes a substrate that includes a bonding pad, a first semiconductor chip disposed on the substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip that is opposite to the substrate, a chip pad disposed on the top surface of the first semiconductor chip, and a bonding wire that connects the chip pad to the bonding pad. The bonding wire includes a first upward protrusion and a second upward protrusion that are convexly curved in a direction away from the substrate. The second semiconductor chip has a first side surface between the first upward protrusion and the second upward protrusion.

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Provided is an optical subassembly, which is compact, is easy to manufacture, and has satisfactory high-frequency characteristics. The optical subassembly includes: an eyelet including a first surface, a second surface and a plurality of through-holes; a plurality of lead terminals; a relay substrate including a lead connection surface and a first bonding surface and having first and second conductor patterns formed across the lead connection surface and the first bonding surface; a device mounting unit including a second bonding surface having formed thereon third and fourth conductor patterns; and an optical device configured to convert one of an optical signal and the differential electrical signals into the other. The first and second conductor patterns on the first bonding surface are connected to the third and fourth conductor patterns by bonding wires, respectively, and the first and second bonding surfaces have normal directions in the same direction.

A leadframe includes a first frame part and a second frame part. The first frame part includes a bed portion including a first section being thin in a first direction, a first support portion, a first lead portion positioned between the bed portion and the first support portion in a second direction, the first lead portion being connected with the bed portion and the first support portion, a first extension portion being connected to the bed portion, and a second extension portion separated from the first extension portion in a third direction and connected to the bed portion. The second frame part includes a second support portion connected to the first and second extension portions, and a second lead portion connected to the second support portion.

A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).

A package is disclosed. In one example the package comprises a carrier having a plurality of leads and an electronic component mounted on the carrier and comprising at least one pad. An impedance structure electrically couples the at least one pad with the carrier so that, at different ones of the leads, different impedance values of the impedance structure can be tapped.

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).