A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe. In some embodiments, singulating the plurality of semiconductor dies comprises performing separate partial cuts of the leadframe.

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.

A method of testing includes attaching a first and second die to first and second die sites of a lead frame and forming a plurality of wire bonds coupling a plurality of pins of the first die site to the first die and a plurality of pins of the second die site to the second die. The first and second die are encapsulated. An isolation cut is performed to isolate the plurality of pins of the first die site from the plurality of pins of the second die site, while maintaining electrical connection between the first tie bar of the first die site and the first tie bar of the second die site. The first and second die are tested while providing a first power supply source to the first and second die via the first tie bars. After testing, the dies sites are fully singulated to result in packaged IC device.

A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.

The present disclosure relates to extremely high frequency (“EHF”) systems and methods for the use thereof, and more particularly to board-to-board connections using contactless connectors.

Embodiments include apparatuses, methods, and systems that may include a leadframe of a circuit package to conduct heat generated by an integrated circuit (IC) included in the circuit package, while being a part of an interconnect of the circuit package. In various embodiments, a circuit package may include a package substrate, and an IC attached to the package substrate. A leadframe may be disposed on the IC to conduct heat generated by the IC. In addition, the leadframe may be a part of an interconnect of the circuit package, and the leadframe may be electrically coupled to a component of the IC. Other embodiments may be described and/or claimed.

A light-emitting apparatus package of the present invention includes (i) an electrically insulated ceramic substrate, (ii) a first concave section formed in the direction of thickness of the ceramic substrate so as to form a light exit aperture in a surface of the ceramic substrate, (iii) a second concave section formed within the first concave section in the further direction of thickness of the ceramic substrate so that one or more light-emitting devices are provided therein, (iv) a wiring pattern for supplying electricity, which is provided in the first concave section, and (v) a metalized layer having light-reflectivity, which is (a) provided between the light-emitting device and the surface of the second concave section of the substrate, and (b) electrically insulated from the wiring pattern. On the account of this, the light-emitting apparatus package in which heat is excellently discharged and light is efficiently utilized and a light-emitting apparatus in which the light-emitting apparatus package is used can be obtained.

A semiconductor module comprises a semiconductor device; a substrate, on which the semiconductor device is attached; a molded encasing, into which the semiconductor device and the substrate are molded; at least one power terminal partially molded into the encasing and protruding from the encasing, which power terminal is electrically connected with the semiconductor device; and an encased circuit board at least partially molded into the encasing and protruding over the substrate in an extension direction of the substrate, wherein the encased circuit board comprises at least one receptacle for a pin, the receptacle being electrically connected via the encased circuit board with a control input of the semiconductor device.

A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled to the wide bandgap semiconductor device, and a first electrode electrically coupled to the wide bandgap semiconductor device and positioned between the wide bandgap semiconductor device and the semiconductor cooling chip. The semiconductor cooling chip is positioned between a substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet port and the substrate outlet port and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more cooling chip fluid channels extending into the semiconductor cooling chip.

A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.