Patent classifications
H01L2224/48106
Waterproof electronic device and manufacturing method thereof
A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.
Semiconductor package
A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.
Semiconductor device with stacking chips
A semiconductor device includes a first chip, a spacer, and a second chip. The first chip and the spacer are disposed on a substrate. The second chip has a first half end portion disposed on a first half end portion of the first chip, and a second half end portion disposed on the spacer. The height of the spacer is substantially equal to the height of the first chip.
Integrated device packages with passive device assemblies
An integrated device package is disclosed. The package can include a package substrate and an integrated device die having active electronic circuitry. The integrated device die can have a first side and a second side opposite the first side. The first side can have bond pads electrically connected to the package substrate by way of bonding wires. A redistribution layer (RDL) stack can be disposed on a the first side of the integrated device die. The RDL stack can comprise an insulating layer and a conductive redistribution layer. The package can include a passive electronic device assembly mounted and electrically connected to the RDL stack.
ELECTRONIC CIRCUIT APPARATUS
There is provided an electronic circuit apparatus in which the heat generated at an electronic component can be transferred to a heat spreader efficiently. An electronic circuit apparatus includes a dielectric substrate, an electronic component, a heat spreader, and a conductive via. The conductive via electrically and thermally connects the electronic component and the heat spreader. The conductive via extends from the first surface to at least an interior of the heat spreader and is in surface-contact with the heat spreader.
POWER SEMICONDUCTOR MODULE AND POWER CONVERSION APPARATUS
A power semiconductor module includes a plurality of self-arc-extinguishing semiconductor elements, a printed wiring board, a plurality of conductive joining members, and a plurality of conductive gate wires. The printed wiring board includes an insulating substrate, a source conductive pattern, and a gate conductive pattern. The plurality of self-arc-extinguishing semiconductor elements each include a source electrode and a gate electrode. The source electrodes are joined to the source conductive pattern by means of the plurality of conductive joining members. The plurality of conductive gate wires connect the gate electrodes and the gate conductive pattern.
Electrical interface for printed circuit board, package and die
A circuit board and package assembly electrically connecting a die to a circuit board. The circuit board has signal paths terminating in a signal pad located on an insulating layer. The circuit board also includes a ground pad on the insulating layer that has a concave shaped side forming a recess, the with a signal pad at least partially within the recess. A package has package ground pads aligned with the circuit board ground pads and package signal pads aligned with circuit board signal pads. The package ground pads extend through the package to connect to package ground paths, which extend toward the die. The package signal pads extend through the package to connect to package signal paths and the package signal paths extend toward the die, maintaining a consistent distance from the package ground paths. Multiple-tier bond wires connect the package bond locations to the die bond pads.
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
In one example, a semiconductor device comprises a cavity substrate comprising a base and a sidewall to define a cavity, an electronic component on a top side of the base in the cavity, a lid over the cavity and over the sidewall, and a valve to provide access to the cavity, wherein the valve has a plug to provide a seal between a cavity environment and an exterior environment outside the cavity. Other examples and related methods are also disclosed herein.
SUBSTRATE WITH INTEGRATED HEAT SPREADER
The present disclosure relates to a substrate with an integrated heat spreader. The disclosed substrate includes a substrate core, at least one connecting structure, and a heat spreader. The substrate core has a top surface and a bottom surface opposite the top surface of the substrate. The at least one connecting structure extends through the substrate core from the top surface of the substrate core to the bottom surface of the substrate core. And the heat spreader extends through the substrate core from the top surface of the substrate core to a bottom level that is below the bottom surface of the substrate core.
WAFER-LEVEL CHIP-SCALE PACKAGE INCLUDING POWER SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF
A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.