Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern including a single via. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first via surrounding a second via. The first and second vias are concentric with one another about a central point of the second via layer.

A semiconductor device, includes: first semiconductor element including first and second electrodes; second semiconductor element including third and fourth electrodes; sealing resin covering the semiconductor elements; first, second, third, and fourth terminal portions respectively connected to the first, second, third, and fourth electrodes and exposed from the sealing resin; first island portion where the first semiconductor element is mounted; and second island portion where the second semiconductor element is mounted, wherein four quadrants divided by first imaginary line extending along second direction orthogonal to first direction and second imaginary line extending along third direction orthogonal to both the first and second directions are defined.

A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

A semiconductor device includes: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; second and third semiconductor chips mounted on the second chip mounting portion; and a sealing body for sealing them. Here, the third semiconductor chip includes a first coil and a second coil that are magnetically coupled to each other. Also, the first coil is electrically connected with a first circuit formed in the first semiconductor chip, and the second coil is electrically connected with a second circuit formed in the second semiconductor chip. Also, in cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil. Further, a power consumption during an operation of the second semiconductor chip is greater than a power consumption during an operation of the first semiconductor chip.

Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.

Semiconductor light-emitting device, includes: substrate having base and conductive part; first to third semiconductor light-emitting elements; first to third wires connected to the first to third semiconductor light-emitting elements respectively; and light-transmitting resin part covering the first to the third semiconductor light-emitting elements, wherein the base has main and rear surfaces facing opposite sides in thickness direction of the base, wherein the conductive part includes main surface part on the main surface, wherein the main surface part includes main surface first part where the first and second semiconductor light-emitting elements are mounted, wherein the main surface first part reaches both ends of the main surface in first direction perpendicular to the thickness direction, and wherein the main surface first part is separated from both the main surface part where the third semiconductor light-emitting element is mounted and the main surface part where the first, second, and third wires are connected.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die. The multiple-path amplifier also may include an integrated phase shifter/impedance inverter coupled between the outputs of the first and second transistors, and which is configured to impart a 90-degree phase delay between intrinsic drains of the first and second transistors.

A semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad.

Disclosed are a semiconductor device and a stacked semiconductor package. The semiconductor device may include a semiconductor chip and a plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; and a second chip pad connected to a diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction.

A semiconductor light emitting device includes a main lead, a sub lead, a semiconductor light emitting element bonded to the main lead, and a protective element bonded to the sub lead, wherein the semiconductor light emitting element is connected to the main lead and the sub lead via a first wire and a second wire, respectively, wherein the protective element has a main surface electrode and a back surface electrode which is connected to the sub lead via a conductive bonding material, and wherein the main surface electrode of the protective element is connected to the main lead via a third wire, a connecting wiring which connects electrodes of the semiconductor light emitting element, and a connecting member including the second wire.