According to one embodiment, a semiconductor device includes a wiring substrate and a first semiconductor chip. The first semiconductor chip has a first surface facing the wiring substrate. The first surface has a groove. The groove extends across the first surface and divides the first surface into a first portion and a second portion. A first bonding layer is between the first portion of the first surface and the wiring substrate. A second bonding layer is between the second portion of the first surface and the wiring substrate. A second semiconductor chip is on the wiring substrate. The second semiconductor chip has a portion inside the groove of the first semiconductor chip. A third bonding layer is between the bottom of the groove and a second surface of the second semiconductor chip.

A semiconductor device includes a signal processing circuit configured to generate an output signal, an output pad, an output line connecting the signal processing circuit to the output pad, the output signal from the signal processing circuit being output from the output pad through the output line, a shorting pad formed in the output line, a switch connected between the shorting pad and the output pad, and configured to connect the signal processing circuit to the output pad when the switch is on, and disconnect the signal processing circuit from the output pad when the switch is off, and a wiring line connecting the shorting pad to the output pad.

A semiconductor device including a first semiconductor switching element having a first gate pad, a plurality of first emitter pads, and a first collector pad, a first wire for connecting adjacent pads out of the plurality of first emitter pads, a first output wire for connecting one of the plurality of first emitter pads to an output, a first controller for applying a gate voltage to the first gate pad, a first emitter wire that is directly connected to a first extraction pad which is any one pad of the plurality of first emitter pads, and is connected to the first controller to give a ground potential of the first controller, and a second semiconductor switching element having a second gate pad, a second emitter pad and a second collector pad connected to the output.

A semiconductor package may include: a package substrate including a plurality of terminals for communication with a memory controller and a plurality of bonding pads for communication inside a package; a buffer chip located on the package substrate; a plurality of memory chips stacked on the buffer chip; and a plurality of wires connecting the plurality of bonding pads and the plurality of memory chips. The buffer chip may communicate with the memory controller through the plurality of terminals of the package substrate, and the plurality of memory chips may communicate with the buffer chip through the plurality of wires and the plurality of bonding pads of the package substrate.

A buffer chip includes: a chip select signal reception circuit configured to receive chip select signals transmitted from a memory controller; a command address reception circuit configured to receive command address signals transmitted from the memory controller; a chip select signal transmission circuit configured to transmit the chip select signals to a plurality of memory chips; a command address transmission circuit configured to transmit the command address signals to the plurality of memory chips; and a command address fixing circuit configured to fix levels of at least one of the command address signals transmitted by the command address transmission circuit when the chip select signals are deactivated for a predetermined time or more.

A semiconductor device includes a semiconductor chip including a first principal surface in which an element region is formed and a peripheral end surface surrounding the first principal surface and an inspection wiring formed along the peripheral end surface on a side of the first principal surface of the semiconductor chip and that surrounds the element region, and, the inspection wiring includes a plurality of internal wiring portions that are formed at a surficial portion of the first principal surface of the semiconductor chip and that are arrayed at a distance from each other along the peripheral end surface of the semiconductor chip and a extending wiring portion that is formed on the first principal surface of the semiconductor chip and that is provided between the internal wiring portions adjoining each other, and the internal wiring portion and the extending wiring portion are alternately arrayed along the peripheral end surface.

A semiconductor device includes the following elements. A chip has a main surface substantially parallel with a plane defined by first and second directions intersecting with each other. A power amplifier amplifies an input signal and outputs an amplified signal from plural output terminals. First and second filter circuits attenuate harmonics of the amplified signal. The first filter circuit includes a first capacitor connected between the plural output terminals and a ground. The second filter circuit includes a second capacitor connected between the plural output terminals and a ground. On the main surface of the chip, the plural output terminals are disposed side by side in the first direction, and the first capacitor is disposed on a side in the first direction with respect to the plural output terminals, while the second capacitor is disposed on a side opposite the first direction with respect to the plural output terminals.

An integrated circuit includes peripheral conductive pads interconnected by a peripheral conductive track within an integrated circuit chip. The integrated circuit chip further includes internal conductive pads interconnected by an internal conductive track within the integrated circuit chip. A conductive bonding wire external to the integrated circuit chip connects the one peripheral conductive pad to one internal conductive pad. A package encapsulates the integrated circuit chip and the conductive bonding wire.

A semiconductor device includes a signal processing circuit configured to generate an output signal, an output pad, an output line connecting the signal processing circuit to the output pad, the output signal from the signal processing circuit being output from the output pad through the output line, a shorting pad formed in the output line, a switch connected between the shorting pad and the output pad, and configured to connect the signal processing circuit to the output pad when the switch is on, and disconnect the signal processing circuit from the output pad when the switch is off, and a wiring line connecting the shorting pad to the output pad.

A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.