A memory device package and a method of manufacturing a memory device package. The memory device package includes a substrate having a first chip region, a second chip region, and a first scribe line region connected between the first chip region and the second chip region. The memory device package also includes a first memory chip disposed over the first chip region and a second memory chip disposed over the second chip region.

A system-in-package (SIP) is described. The SIP includes a general-purpose memory die. The SIP also includes a near-memory compute die. The SIP further includes an inter-space filler in between the general-purpose memory die and the near-memory compute die.

A buffer chip includes: a chip select signal reception circuit configured to receive chip select signals transmitted from a memory controller; a command address reception circuit configured to receive command address signals transmitted from the memory controller; a chip select signal transmission circuit configured to transmit the chip select signals to a plurality of memory chips; a command address transmission circuit configured to transmit the command address signals to the plurality of memory chips; and a command address fixing circuit configured to fix levels of at least one of the command address signals transmitted by the command address transmission circuit when the chip select signals are deactivated for a predetermined time or more.