A semiconductor device includes: semiconductor elements; a package sealing the semiconductor elements and being rectangular in a top view; control terminals protruding from a first side of the package; output terminals protruding from a second side facing the first side of the package; and a recessed portion formed in a third side adjacent to the first side and the second side of the package, wherein a part of the control terminals is disposed at end portions of lead frames, the semiconductor device further includes dummy terminals disposed at other end portions of the lead frames, respectively, the dummy terminals protruding from the recessed portion, and an amount of the protrusion of each of the dummy terminals from the recessed portion is smaller than or equal to 0.75 mm.

Embodiments of RF amplifiers and packaged RF amplifier devices each include an amplification path with a transistor die, and an output-side impedance matching circuit having a T-match circuit topology. The output-side impedance matching circuit includes a first inductive element (e.g., first wirebonds) connected between the transistor output terminal and a quasi RF cold point node, a second inductive element (e.g., second wirebonds) connected between the quasi RF cold point node and an output of the amplification path, and a first capacitance connected between the quasi RF cold point node and a ground reference node. The RF amplifiers and devices also include a baseband termination circuit connected to the quasi RF cold point node, which includes an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the quasi RF cold point node and the ground reference node.

According to one embodiment, a semiconductor device includes an integrated circuit (IC) chip and a silicon capacitor. The IC chip has a first terminal and a second terminal on a first surface. The silicon capacitor has a first electrode and a second electrode on a second surface facing the first surface. The first electrode is electrically connected to the first terminal through a first conductive member, and the second electrode is electrically connected to the second terminal through a second conductive member.

A light emitting device includes: a base member having a first surface including a first region; a first electric terminal including a first pin hole, the first pin hole penetrating the base member along a thickness direction of the base member; a second electric terminal including a second pin hole, the second pin hole penetrating the base member along the thickness direction; a first frame provided on the base member and surrounding the first region; a plurality of light emitting elements provided on the base member in the first region; a light-transmissive first member provided inward of the first frame, and covering the plurality of light emitting elements; and a protective element positioned between the base member and the first frame in the thickness direction. When viewed in a direction from the first pin hole toward the second pin hole, the protective element is positioned between the plurality of light emitting elements and the first pin hole and between the plurality of light emitting elements and the second pin hole.

A semiconductor device includes first semiconductor chips that each include a first control electrode and a first output electrode, second semiconductor chips each include a second control electrode and a second output electrode, first and second input circuit patterns on which the first and second input electrodes are disposed, respectively, first and second control circuit patterns electrically connected to the first and second control electrodes, respectively, first and second resistive elements, and a first inter-board wiring member. The first control electrodes and first resistive element are electrically connected via the first control circuit pattern, the second control electrodes and second resistive element are electrically connected via the second control circuit pattern, and at least one of the first output electrodes and at least one of the second output electrodes are electrically connected to each other via the first inter-board wiring member.

A semiconductor package includes a first set of leads, a temperature sensor proximate the first set of leads, a second set of leads, a semiconductor die, a first electrical connection between the temperature sensor and the semiconductor die, a second electrical connection between the semiconductor die and the second set of leads, and mold compound at least partially covering the temperature sensor, the semiconductor die, the first set of leads and the second set of leads. The mold compound physically separates the semiconductor die from the temperature sensor and the first set of leads.

An electrostatic discharge (ESD), protection device is provided. In accordance with the present disclosure, an ESD protection device is provided that includes a series connection of a first unit having strong snapback and low series capacitance and a second high-voltage unit that displays a relatively high holding/trigger voltage to ensure latch up and improper triggering of the ESD protection device while at the same time providing high-voltage operation with low capacitive loading.

A semiconductor assembly includes a semiconductor switching device, a conductive load base structure, and a current sense unit. The semiconductor switching device includes a drain structure and one or more array units, wherein each array unit includes a load pad and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure. The current sense unit is electrically connected between a first one of the load pads and the load base structure.

Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

A module arrangement for power semiconductor devices, includes two or more heat spreading layers with a first surface and a second surface being arranged opposite to the first surface. At least two or more power semiconductor devices are arranged on the first surface of the heat spreading layer and electrically connected thereto. An electrical isolation stack comprising an electrically insulating layer and electrically conductive layers is arranged in contact with the second surface of each heat spreading layer. The at least two or more power semiconductor devices, the heat spreading layers and a substantial part of each of the electrical isolation stacks are sealed from their surrounding environment by a molded enclosure. Accordingly, similar or better thermal characteristic of the module can be achieved instead of utilizing high cost electrically insulating layers, and double side cooling configurations can be easily implemented, without the use of a thick baseplate.