A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.

A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.

A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.

An intelligent power module, which includes: a lead frame; a plurality of signal processing chips, disposed on the lead frame; at least one bridge die, configured to operably transmit signals among the signal processing chips; and a package structure, encapsulating the lead frame, the signal processing chips and the bridge die.

A semiconductor device includes an insulating member; a light-receiving element on a front surface of the insulating member; a light-emitting element on the light-receiving element; a first metal terminal electrically connected to the light-emitting element and provided on a back surface of the insulating member; a switching element mounted on the front surface via a metal pad, the switching element being electrically connected to the light-receiving element; and a second metal terminal provided on the back surface and electrically connected to the switching element via the metal pad. The insulating member has a first thickness in a first direction directed from the back surface toward the front surface. The metal pad has a second thickness in the first direction. The second metal terminal has a third thickness in the first direction. The first thickness is less than a combined thickness of the second and third thicknesses.

An intelligent power module includes: an encapsulating material structure; a lead frame which is at least partially encapsulated inside the encapsulating material structure, wherein all portions of the lead frame encapsulated inside the encapsulating material structure are at a same planar level; and a heat dissipation structure, which is connected to the lead frame.

A semiconductor apparatus includes: a first semiconductor chip; a resin enclosure having a space in which the first semiconductor chip is positioned; a lead terminal disposed in the resin enclosure; a second semiconductor chip configured to: control the first semiconductor chip, and be disposed on a first portion of the resin enclosure, the resin enclosure not overlapping with the lead terminal, as seen in planar view from a direction perpendicular to a top surface of the lead terminal; and a wire having a first end connected to the lead terminal and a second end connected to the second semiconductor chip.

An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

A transistor package that includes a metal submount; a transistor die mounted on said metal submount; a surface mount IPD component that includes a dielectric substrate; and the dielectric substrate mounted on said metal submount. Additionally, the dielectric substrate includes one of the following: an irregular shape, a non-square shape, and a nonrectangular shape.