An electronic device includes a package structure, conductive leads, first and second semiconductor dies, and a metal clip, The package structure has opposite longitudinal ends, opposite lateral sides, a middle portion midway between the longitudinal ends, a first portion that extends between the middle portion and one longitudinal end, and a second portion that extends between the middle portion and the other longitudinal end. The metal clip extends in the package structure from the first portion to the second portion through the middle portion and electrically couples the first electronic component of the first semiconductor die to the second electronic component of the second semiconductor die.

A microelectronic device includes a die pad having a first surface and a second, opposite, surface. A first component is directly attached to the first surface of the die pad through a first thermally conductive material. A second component is directly attached to the second surface of the die pad through a second thermally conductive material. At least a portion of the second component overlaps at least a portion of the first component. The microelectronic device further includes a first thermal shunt connecting the die pad to a first lead, and a second thermal shunt connecting the die pad to a second lead. The first thermal shunt is closer to a center of the first component than to a center of the second component. The second thermal shunt is closer to a center of the second component than to a center of the first component.

An integrated circuit (IC) package and assembly includes a stacked arrangement of one or more IC die to leverage additional functionality in a standard package width. Active IC die and high voltage IC capacitors may be stacked in various arrangements to minimize the footprint and width of the IC package. The die are interconnected with each other and a lead frame with wire bonds, silicon vias or other interconnections. Various bond pad configurations are used to interconnect the die. The stacked arrangement of the IC die reduces the width of the supporting lead frame and reduces the overall footprint of the IC package.