An electronic device includes a package structure, a first lead and a second lead. The first lead has a first portion extending outward from a side of the package structure and downward, and a second portion extending outward from the first portion away from the package side. The second lead has a first portion extending outward from the package side and downward, and a second portion extending inward from the first portion toward the package side, and a distal end of the second lead is spaced from the package side.

Electromagnetic shields for electronic devices, and particularly electromagnetic shields with bonding wires for sub-modules of electronic devices are disclosed. Electronic modules are disclosed that include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged on or over the sub-modules. Bonding wires are disclosed that form one or more bonding wire walls along the substrate. The one or more bonding wire walls may be located between sub-modules of a module and about peripheral boundaries of the module. The electromagnetic shield may be electrically coupled to ground by way of the one or more bonding wire walls. Portions of the electromagnetic shield and the one or more bonding wire walls may form divider walls that are configured to reduce electromagnetic interference between the sub-modules or from external sources.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

A semiconductor module includes: a case; a semiconductor chip provided inside the case; a seal material injected to inside of the case and sealing the semiconductor chip; and a lid provided inside the case and contacting an upper surface of the seal material, wherein a tapered portion is provided at an end portion of the lid on an upper surface side, a gap is provided between a side surface of the end portion of the lid and an inner side surface of the case, and the seal material crawls up to the tapered portion through the gap.

The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

Disclosed herein is an integrated circuit (IC) comprising a semiconductor wafer, a dielectric layer, and an isolation element. The semiconductor wafer has a first wafer portion and a second wafer portion each extending from a frontside surface to a backside surface. The dielectric layer interfaces with the first wafer portion and with the second wafer portion each on the frontside surface. The isolation element has an isolation dielectric material, and the isolation element extends between a first side surface of the first wafer portion and a second side surface of the second wafer portion and from an extension plane of the frontside surface to an extension plane of the backside surface. Also disclosed herein is a system comprising the IC and a package substrate coupled to the IC.

The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.

A described example includes: a MEMS component on a device side surface of a first semiconductor substrate; a second semiconductor substrate bonded to the device side surface of the first semiconductor substrate by a first seal patterned to form sidewalls that surround the MEMS component; a third semiconductor substrate having a second seal extending from a surface and bonded to the backside surface of the first semiconductor substrate by the second seal, the second seal forming sidewalls of a gap beneath the MEMS component. A trench extends through the first semiconductor substrate and at least partially surrounds the MEMS component. The third semiconductor substrate is mounted on a package substrate. A bond wire or ribbon bond couples the bond pad to a conductive lead on the package substrate; and mold compound covers the MEMS component, the bond wire, and a portion of the package substrate.