H01L2224/48464

Integrated circuit package assembly

An integrated circuit package assembly includes a substrate and a first integrated circuit package over the substrate. The integrated circuit package assembly also includes a second integrated circuit package between the first integrated circuit package and the substrate. The integrated circuit package further includes solder bumps between the first integrated circuit package and the second integrated circuit package. The solder bumps are configured to electrically connect the first integrated circuit package and the second integrated circuit package. The integrated circuit package assembly further includes at least two support structures between and in direct contact with the second integrated circuit package and the substrate. The at least two support structures are configured to facilitate thermal conduction between the second integrated circuit package and the substrate without providing electrical connections.

LIGHT-EMITTING DIODE LIGHT SOURCE AND LAMP
20170248277 · 2017-08-31 ·

A light-emitting diode (LED) light source includes a plurality of electricity-conducting holding elements, and each electricity-conducting holding element is made of a thin metal sheet. The bendable LED light source increases installation of sufficient number of LED dies by lengthening the length of the LED light source. The LED light source is bent to form a spring-like helical structure and then is placed inside a lamp cover. The helical LED light source is fastened on a T-shaped element by a plurality of fastening elements and the T-shaped element is fixed on an insulated holder. Accordingly, a bulb-type LED lamp is implemented.

Stacking arrangement for integration of multiple integrated circuits

A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

Stacking arrangement for integration of multiple integrated circuits

A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

Integrated Back Light Unit Including Non-Uniform Light Guide Unit

An integrated back light unit can include a light guide plate having a non-uniform distribution of extraction features. The non-uniform distribution of the extraction features can be provided by an extraction-feature-free region in proximity to a light emitting device, and/or by a variable density of the extraction features that changes with distance from the light emitting device. Additionally or alternatively, the light guide unit can include a heterogeneous reflectivity surface that has a different reflectivity at proximity to the light emitting device assembly than at a distal portion of the light guide unit. The different reflectivity may be provided by a specular reflective material, diffusive reflective material, or a light absorbing material. The non-uniform distribution of extraction features and/or the heterogeneous reflectivity surface can be employed to enhance brightness uniformity of the reflective light and/or to control the temperature distribution within the light guide unit.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
20170236772 · 2017-08-17 · ·

A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has amounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads.

Packaged semiconductor device having a shielding against electromagnetic interference and manufacturing process thereof

A packaged device has a die of semiconductor material bonded to a support. An electromagnetic shielding structure surrounds the die and is formed by a grid structure of conductive material extending into the support and an electromagnetic shield, coupled together. A packaging mass embeds both the die and the electromagnetic shield. The electromagnetic shield is formed by a plurality of metal ribbon sections overlying the die and embedded in the packaging mass. Each metal ribbon section has a thickness-to-width ratio between approximately 1:2 and approximately 1:50.

Semiconductor device and method for manufacturing the same

An object of the present invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on the element formation layer, and a conductive film serving as an antenna, which is provided on the insulating film. The insulating film has a groove. The conductive film is provided along the surface of the insulating film and the groove. The groove of the insulating film may be provided to pass through the insulating film. Alternatively, a concave portion may be provided in the insulating film so as not to pass through the insulating film. A structure of the groove is not particularly limited, and for example, the groove can be provided to have a tapered shape, etc.

SEMICONDUCTOR DEVICE
20220037488 · 2022-02-03 ·

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor chip having a first main surface including an active region and a peripheral region surrounding the active region; a first trench formed in the active region; a first insulating film formed on an inner surface of the first trench; a first electrode formed in the first trench interfacing the first insulating film, and forming a channel in a portion of the semiconductor chip facing the first insulating film; a second trench formed in the peripheral region and having a width greater a width of the first trench; a second insulating film formed on an inner surface of the second trench; and a second electrode formed in the second trench interfacing the second insulating film and electrically coupled to the first electrode.

Chip-scale package and semiconductor device assembly

A chip-scale package for an edge-emitting semiconductor device and a semiconductor device assembly including such a chip-scale package are provided. The chip-scale package includes an edge-emitting semiconductor device chip, a top submount disposed on a top surface of the chip, and a bottom submount disposed on a bottom surface of the chip. The top-submount area and the bottom-submount area are each greater than the chip area and less than or equal to about 1.2 times the chip area.