A semiconductor package structure, including a lead frame, a die disposed on the front side of the lead frame, and a molding piece disposed on the lead frame and encapsulates the die, wherein the lead frame is provided with two extension portions extending respectively from two sides of the molding piece, and the extension portion is provided with recessed front surface and back surface on which a plating layer is formed.

A wire bonding method includes bonding a tip of a wire provided through a clamp and a capillary onto a bonding pad of a chip, moving the capillary to a connection pad of a substrate corresponding to the bonding pad, bonding the wire to the connection pad to form a bonding wire connecting the bonding pad to the connection pad, before the capillary is raised from the connection pad, applying a electrical signal to the wire to detect whether the wire and the connection pad are in contact with each other, changing a state of the clamp to a closed state when the wire is not in contact with the connection pad and maintaining the state of the clamp in an open state when the wire is in contact with the connection pad, and raising the capillary from the connection pad while maintaining the state of the clamp.

In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.

An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a QFN device when it is attached to a printed wiring board (PWB).

An optical device includes a substrate including an optical waveguide running through the substrate. An optical transmitter mounted on the substrate in a first location includes at least one optical emitter, which emits a primary beam of optical radiation toward a target and emits a secondary beam of the optical radiation into the optical waveguide. An optical receiver mounted on the substrate in a second location includes at least one optical sensor, which receives the optical radiation that is reflected from the target and outputs a primary signal in response thereto, and receives the secondary beam of the optical radiation from the waveguide and outputs a reference signal in response to the secondary beam. A processor receives and processes the primary signal and the reference signal in order to extract information with respect to the target.

A semiconductor device includes a semiconductor element, a support member, and a bonding layer interposed between the semiconductor element and the support member, wherein the bonding layer contains an alloy of first metal and second metal.

A semiconductor device includes: a semiconductor element; a support member; a bonding layer interposed between the semiconductor element and the support member; and a sealing resin that covers the semiconductor element and at least a portion of the support member, wherein the bonding layer is a layer in which a layer containing first metal and a layer containing second metal are integrated without going through a molten state, and wherein the support member includes a first surface facing in a thickness direction and facing a side on which the semiconductor element is located, and a plurality of first recesses located outside the bonding layer and recessed from the first surface when viewed along the thickness direction.

The present invention provides a light emitting element capable or realizing at least one of lower resistance, higher output, higher power efficiency (1 m/W), higher mass productivity and lower cost of the element using a light transmissive electrode for an electrode arranged exterior to the light emitting structure. A semiconductor light emitting element includes a light emitting section, a first electrode and a second electrode on a semiconductor structure including first and second conductive type semiconductor layers, the first and the second electrodes respectively including at least two layers of a first layer of a light transmissive conductive film conducting to the first and the second conductive type semiconductor and a second layer arranged so as to conduct with the first layer. First and second light transmissive insulating films are respectively arranged so as to overlap at least one part of the first and the second layers.

The present invention provides a light emitting element capable or realizing at least one of lower resistance, higher output, higher power efficiency (1 m/W), higher mass productivity and lower cost of the element using a light transmissive electrode for an electrode arranged exterior to the light emitting structure. A semiconductor light emitting element includes a light emitting section, a first electrode and a second electrode on a semiconductor structure including first and second conductive type semiconductor layers, the first and the second electrodes respectively including at least two layers of a first layer of a light transmissive conductive film conducting to the first and the second conductive type semiconductor and a second layer arranged so as to conduct with the first layer. First and second light transmissive insulating films are respectively arranged so as to overlap at least one part of the first and the second layers.

A packaged micro-electro-mechanical system (MEMS) device (100) comprises a circuitry chip (101) attached to the pad (110) of a substrate with leads (111), and a MEMS (150) vertically attached to the chip surface by a layer (140) of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring (130) with a surface phobic to silicone compounds. A dome-shaped glob (160) of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (180); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package (190) of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.