A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

A light emitting device includes a base member including a conductive member; a light mining element arranged on the base member, the light emitting element having a first surface, a second surface opposing the first surface, and at least one lateral surface between the first surface and the second surface; a die-bonding resin bonding the base member and the second surface; a first protective film continuously covering the base member, the die-bonding resin, the at least one lateral surface, and the first surface; and a second protective film continuously covering the base member, the die-bonding resin, the at least one lateral surface and the first surface of the light emitting element, over the first protective film, the second protective film having a linear expansion coefficient that is smaller than a linear expansion coefficient of the die-bonding resin and larger than a linear expansion coefficient of the first protective film.

A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

A multi-chip package may include a package substrate including a first substrate pad and a second substrate pad, first semiconductor chips stacked on the package substrate in a steplike shape along a first direction, second semiconductor chips stacked on the first semiconductor chips in a steplike shape along a second direction opposite the first direction, first pad wires electrically connecting first bonding pads of the first semiconductor chips with each other, second pad wires electrically connecting second bonding pads of the second semiconductor chips with each other, a first substrate wire electrically connecting the first substrate pad with a first bonding pad of any one among the first semiconductor chips except for a lowermost first semiconductor chip, and a second substrate wire electrically connecting the second substrate pad with a second bonding pad of any one among the second semiconductor chips except for a lowermost second semiconductor chip.

A housing for an optical component is provided in various embodiments. The housing has a leadframe section and a mold compound. The leadframe section is formed from an electrically conductive material and has a first side and a second side facing away from the first side. On the first side, the leadframe section has at least one first receiving region for receiving the optical component and/or at least one contact region for electrically contacting the optical component. The leadframe section has at least one trench which is formed in the leadframe section on the first side thereof alongside the receiving region and/or the contact region. The leadframe section is embedded in the mold compound. The mold compound has at least one receiving recess in which the first receiving region and/or the contact region and the trench are arranged.

An optoelectronic semiconductor component includes a carrier and at least one optoelectronic semiconductor chip mounted on the carrier top. The semiconductor component includes at least one bonding wire, via which the semiconductor chip is electrically contacted, and at least one covering body mounted on a main radiation side and projects beyond the bonding wire. At least one reflective potting compound encloses the semiconductor chip laterally and extends at least as far as the main radiation side of the semiconductor chip. The bonding wire is covered completely by the reflective potting compound or completely by the reflective potting compound together with the covering body.

An optoelectronic semiconductor component includes a carrier and at least one optoelectronic semiconductor chip mounted on the carrier top. The semiconductor component includes at least one bonding wire, via which the semiconductor chip is electrically contacted, and at least one covering body mounted on a main radiation side and projects beyond the bonding wire. At least one reflective potting compound encloses the semiconductor chip laterally and extends at least as far as the main radiation side of the semiconductor chip. The bonding wire is covered completely by the reflective potting compound or completely by the reflective potting compound together with the covering body.