Patent classifications
H01L2224/48472
Multi-layer interconnection ribbon
A semiconductor package assembly includes a carrier with a die attach surface and a contact pad separated from the die attach surface, a semiconductor die mounted on the die attach surface, the semiconductor die having a front side metallization that faces away from the die attach surface, an interconnect ribbon attached to the semiconductor die and the contact pad such that the interconnect ribbon electrically connects the front side metallization to the contact pad, and an electrically insulating encapsulant body that encapsulates the semiconductor die and at least part of the interconnect ribbon. The interconnect ribbon includes a layer stack of a first metal layer and a second layer formed on top of the first metal layer. The first metal layer includes a different metal as the second metal layer. The first metal layer faces the front side metallization.
Semiconductor Power Module with Two Different Potting Materials and a Method for Fabricating the Same
A semiconductor power module comprises an insulating interposer comprising an insulative layer disposed between a lower metal layer, a first upper metal layer and a second upper metal layer, a semiconductor transistor die disposed on the first upper metal layer, an electrical connector connecting the semiconductor transistor die with the second upper metal layer, a housing enclosing the insulating interposer and the semiconductor transistor die, a first potting material covering at least selective portions of the semiconductor transistor die and the electrical connector; and a second potting material applied onto the first potting material, wherein the first and second potting materials are different from each other.
Power semiconductor module arrangement
A power semiconductor module arrangement includes: a housing; first and second electrical contacts within the housing; and a mounting arrangement including a frame or body and first and second terminal elements. The mounting arrangement is inserted in and coupled to the housing. First ends of the first and second terminal elements mechanically and electrically contact the first and second electrical contacts, respectively. A middle part of each terminal element extends through the frame or body. A second end of each terminal element extends outside the housing. The first terminal element is dielectrically insulated from the second terminal element by a portion of the frame or body. The first terminal element is injected into and inextricably coupled to the frame or body. The second terminal element is arranged within a hollow space inside the frame or body and is detachably coupled to the frame or body.
High power multilayer module having low inductance and fast switching for paralleling power devices
A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices. The power module further including a base plate and a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module.
Semiconductor device and method for manufacturing semiconductor device
A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the lead frame, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.
POWER MODULE AND POWER CONVERSION DEVICE
A power module includes an insulating substrate, a case member, a power semiconductor element, a base member, a sealing member, and an adhesive member. The insulating substrate has a first surface and a second surface opposite to the first surface. The case member surrounds the insulating substrate when viewed in a direction perpendicular to the first surface. The power semiconductor element faces the first surface. The base member faces the second surface. The sealing member seals the power semiconductor element and the insulating substrate and is in contact with the case member. The adhesive member fixes the base member and the case member, and surrounds the insulating substrate when viewed in the direction perpendicular to the first surface.
Semiconductor module arrangement
A semiconductor module arrangement includes a housing and at least one pair of semiconductor substrates arranged inside the housing. Each pair of semiconductor substrates includes first and second semiconductor substrates. The first semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The second semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential, and the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential that is opposite to the first electrical potential.
Power Semiconductor Module with Laser-Welded Leadframe
A power semiconductor module includes a substrate with a structured metallization layer and a number of semiconductor chips. Each chip has a first power electrode bonded to the metallization layer. A leadframe is laser-welded to second power electrodes of the semiconductor chips for electrically interconnecting the semiconductor chips. A control conductor is attached to the leadframe opposite to the semiconductor chips and is electrically isolated from the leadframe. The control conductor is electrically connected to control electrodes of the semiconductor chips in the group.
CONDUCTIVE METAL FRAME FOR A POWER ELECTRONIC MODULE AND ASSOCIATED MANUFACTURING PROCESS
A conductive metal frame for a power electronics module comprising at least first and second power semiconductor components each having upper and lower faces, connectors for linking these power semiconductor components to external electrical circuits and at least one radiator for expelling via the conductive metal frame the heat flow generated by the power semiconductor components, the conductive metal frame being characterized in that the connectors, the at least one radiator and the conductive metal frame forming a single three-dimensional part made of a single material on an inner surface of which the first and second power semiconductor components are intended to be attached by their lower faces and provision is made for a central folding line so that, once the conductive metal frame is folded on itself, enclosing the first and second power semiconductor components, it provides a double-sided cooling assembly.
SEMICONDUCTOR APPARATUS
A semiconductor apparatus includes: a first semiconductor chip; a resin enclosure having a space in which the first semiconductor chip is positioned; a lead terminal disposed in the resin enclosure; a second semiconductor chip configured to: control the first semiconductor chip, and be disposed on a first portion of the resin enclosure, the resin enclosure not overlapping with the lead terminal, as seen in planar view from a direction perpendicular to a top surface of the lead terminal; and a wire having a first end connected to the lead terminal and a second end connected to the second semiconductor chip.