A semiconductor package includes a substrate and a semiconductor chip, a lower conductive layer and an upper conductive layer sequentially stacked on the substrate. The substrate includes first and second connection pads formed thereon. The semiconductor chip includes third and fourth connection pads formed thereon. The upper conductive layer is connected to the first and the third connection pads via a first and a second wiring, and the lower conductive layer is connected to the second and the fourth connection pads via a third and a fourth wiring.

A semiconductor package includes a substrate and a semiconductor chip, a lower conductive layer and an upper conductive layer sequentially stacked on the substrate. The substrate includes first and second connection pads formed thereon. The semiconductor chip includes third and fourth connection pads formed thereon. The upper conductive layer is connected to the first and the third connection pads via a first and a second wiring, and the lower conductive layer is connected to the second and the fourth connection pads via a third and a fourth wiring.

A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.

First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.

A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

A semiconductor module includes a substrate, a semiconductor element, and a wire. The semiconductor element is joined onto the substrate and has a surface electrode. Both ends of the wire are bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element. The wire is electrically connected to the surface electrode.

A semiconductor module includes a substrate, a semiconductor element, and a wire. The semiconductor element is joined onto the substrate and has a surface electrode. Both ends of the wire are bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element. The wire is electrically connected to the surface electrode.