A flip-chip LED chip includes: a substrate; a first semiconductor layer; a light emitting layer; a second semiconductor layer; a local defect region over part of the second semiconductor layer and extending downward to the first semiconductor layer; first and second metal layers respectively over portions of the first and second semiconductor layers; an insulating layer covering the first and second metal layers, the second and first semiconductor layers in the local defect region. The insulating layer has opening structures over the first and second metal layers respectively; a eutectic electrode structure over the insulating layer with openings and including first and second eutectic layers from bottom up at a vertical direction, and including first-type and second-type electrode regions at a horizontal direction. The second eutectic layer does not overlap with the first and second metal layers at the vertical direction.

A methodology and medium for regular and predictable cleaning the support hardware such as capillary tube in semiconductor assembly equipment components, while it is still in manual, semi-automated, and automated assembly are disclosed. The cleaning material may include a cleaning pad layer and one or more intermediate layers that have predetermined characteristics.

A Flip-chip LED chip includes: a substrate; a first semiconductor layer; a second semiconductor layer; a local defect region over part of the second semiconductor layer, which extends downward to the first semiconductor layer; a first metal layer over part of the first semiconductor layer; a second metal layer over part of the second semiconductor layer; an insulating layer covering the first metal layer, the second metal layer, the second semiconductor layer and the first semiconductor layer in the local defect region, with opening structures over the first metal layer and the second metal layer respectively; an eutectic electrode structure over the insulating layer, including a first eutectic layer and a second eutectic layer at vertical direction, and a first-type electrode region and a second-type electrode region at horizontal direction. Poor packaging caused by high eutectic void content during eutectic bonding process can therefore be reduced.

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

A methodology and medium for regular and predictable cleaning the support hardware such as capillary tube in semiconductor assembly equipment components, while it is still in manual, semi-automated, and automated assembly are disclosed. The cleaning material may include a cleaning pad layer and one or more intermediate layers that have predetermined characteristics.

In a soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member, void generation is prevented and solder wettability is improved. The soldering method for Ag-containing lead-free solders of the present invention is a soldering method for Ag-containing lead-free solders includes a first step of bringing a lead-free solder having a composition that contains Ag that a relation between a concentration C (mass %) of Ag contained in an SnAg-based lead-free solder before soldering of a mass M(g) and an elution amount B(g) of Ag contained in the Ag-containing member becomes 1.0 mass %(MC+B)100/(M+B)4.6 mass % and that the balance consists of Sn and unavoidable impurities into contact with the Ag-containing member, a second step of heating and melting the lead-free solder, and a third step of cooling the lead-free solder.

A Flip-chip LED chip includes: a substrate; a first semiconductor layer; a second semiconductor layer; a local defect region over part of the second semiconductor layer, which extends downward to the first semiconductor layer; a first metal layer over part of the first semiconductor layer; a second metal layer over part of the second semiconductor layer; an insulating layer covering the first metal layer, the second metal layer, the second semiconductor layer and the first semiconductor layer in the local defect region, with opening structures over the first metal layer and the second metal layer respectively; an eutectic electrode structure over the insulating layer, including a first eutectic layer and a second eutectic layer at vertical direction, and a first-type electrode region and a second-type electrode region at horizontal direction. Poor packaging caused by high eutectic void content during eutectic bonding process can therefore be reduced.

In a soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member, void generation is prevented and solder wettability is improved. The soldering method for Ag-containing lead-free solders of the present invention is a soldering method for Ag-containing lead-free solders includes a first step of bringing a lead-free solder having a composition that contains Ag that a relation between a concentration C (mass %) of Ag contained in an SnAg-based lead-free solder before soldering of a mass M(g) and an elution amount B(g) of Ag contained in the Ag-containing member becomes 1.0 mass %(MC+B)100/(M+B)4.6 mass % and that the balance consists of Sn and unavoidable impurities into contact with the Ag-containing member, a second step of heating and melting the lead-free solder, and a third step of cooling the lead-free solder.