Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/42
Wire connectors; Manufacturing methods related thereto
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H01L2224/47
Structure, shape, material or disposition of the wire connectors after the connecting process
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H01L2224/48
of an individual wire connector
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H01L2224/4899
Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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H01L2224/48991
being formed on the semiconductor or solid-state body to be connected
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H01L2224/48993

COMPACT WIREBONDING IN STACKED-CHIP SYSTEM IN PACKAGE, AND METHODS OF MAKING SAME
20190181072 · 2019-06-13 ·

A bond-wire system including a wire bond that is deflected above a dielectric ridge at a die edge. The deflected wire bond allows for both a lowered Z-profile and a reduced X-Y footprint. The bond-wire system may include a stacked-die configuration where a stacked die is wire bonded and the stacked-die bond wire is deflected above a dielectric ridge at the stacked die edge.