The instant disclosure provides an integrated circuit device including a transmission line which includes a first ground line and a signal line. The first ground line includes a first pad, a second pad and a first bonding wire that is a bond wire structure connecting the first pad and the second pad. The first signal line includes a third pad, a fourth pad and a second bonding wire that is a bond wire structure connecting the third pad and the fourth pad.

A multi-chip package may include a package substrate including a first substrate pad and a second substrate pad, first semiconductor chips stacked on the package substrate in a steplike shape along a first direction, second semiconductor chips stacked on the first semiconductor chips in a steplike shape along a second direction opposite the first direction, first pad wires electrically connecting first bonding pads of the first semiconductor chips with each other, second pad wires electrically connecting second bonding pads of the second semiconductor chips with each other, a first substrate wire electrically connecting the first substrate pad with a first bonding pad of any one among the first semiconductor chips except for a lowermost first semiconductor chip, and a second substrate wire electrically connecting the second substrate pad with a second bonding pad of any one among the second semiconductor chips except for a lowermost second semiconductor chip.

A transistor amplifier package includes a base, one or more transistor dies on the base, first and second leads coupled to the one or more transistor dies and defining respective radio frequency (RF) signal paths, and an isolation structure on the base between the respective RF signal paths. The isolation structure includes first and second wire bonds. The first and second wire bonds may have a crossed configuration defining at least one cross point therebetween. Related wire bond-based isolation structures are also discussed.

A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation.

A light-emitting diode (LED) package includes a first LED pixel including a plurality of first LED chips and a first pixel driving integrated circuit to drive the first LED chips according to an active matrix (AM) mode using entirety of a first frame period, wherein the first pixel driving integrated circuit includes a first storage area configured to store first frame data of each first LED chip, a second storage area configured to store duty ratio compensation data of each first LED chip, a pulse width modulation (PWM) data calculator configured to perform an arithmetic operation on the first frame data and the duty ratio compensation data to generate PWM data, and a PWM data generator configured to adjust an emission duty ratio based on the PWM data.

A deteriorated section identifying unit refers to correspondence information that defines a deteriorated section of a plurality of bonding sections to the emitter electrode surface to which the first bonding wires are connected, for a combination of temporal change of a first voltage that is a difference between a potential at a collector main terminal and a potential at the emitter main terminal and temporal change of a second voltage that is a difference between a potential at the emitter reference terminal and a potential at the emitter main terminal, and identifies the deteriorated section corresponding to a combination of temporal change of the first voltage measured by a first voltage measuring circuit and temporal change of the second voltage measured by a second voltage measuring circuit.

The present disclosure provides a semiconductor a semiconductor device package includes a substrate, an electronic component disposed on the substrate, a package body disposed on the substrate and encapsulating the electronic component, and a capacitor disposed above the electronic component. The capacitor is exposed from the package body.

Example embodiments relate to RF amplifier packages. One example RF amplifier package includes an input terminal, an output terminal, a substrate, a first DC blocking capacitor having a first terminal and a grounded second terminal, and a second conductor die mounted on the substrate. The semiconductor die includes a semiconductor substrate, an RE power field-effect transistor (FET) integrated on the semiconductor substrate, a gate bondbar, a first drain bondbar, a second drain bondbar, and a plurality of first bondwires connecting the second drain bondbar to the first terminal of the first DC blocking capacitor. The RF power FET includes a plurality of gate fingers that are electrically connected to the gate bondbar and that each extend from the gate bondbar towards the first drain bondbar and underneath the second drain bondbar, a first set of drain fingers, and a second set of drain fingers.

A module includes: a board having a first surface; a first component and a second component mounted on the first surface; and a wire disposed to extend across the first component and having one end and the other end. The one end is connected to the second component. The wire is grounded.

In one aspect of the semiconductor module, the sealing material on the lower side of the die stage is thinner than the sealing material on the upper side of the semiconductor element, a bent portion that forms a step with respect to vertical direction in the first lead is provided in a region sealed by the sealing material in the first lead, the side where the die stage is present of the step is positioned below the side where the die stage is not present of the step due to the step, the side where the die stage is not present of the step in the first lead protrudes from one end side of the sealing material, and a groove is provided on an upper side surface, a lower side surface, or both of them of the bent portion of the first lead.