A semiconductor package includes a carrier, a package module and a second package body. The package module is disposed on the carrier and includes a first substrate, a first electronic element, a first conductive wire and a first package body. The first substrate has a first electrical surface facing the carrier and a second electrical surface opposite to the first electrical surface. The first electronic element is disposed on the first electrical surface. The first conductive wire connects the electronic element with the first electrical surface of the first substrate. The first package body encapsulates the first electrical surface, the first electronic element and the first solder wire. The second package body encapsulates the package module and a portion of the carrier.

A semiconductor device, including a substrate having an insulating layer and a plurality of circuit patterns formed on the insulating layer, the substrate having a principal surface on which an element region is set. The semiconductor device further includes a plurality of semiconductor elements provided on the plurality of circuit patterns in the element region, a plurality of main terminals that each have a first end joined to one of the plurality of circuit patterns in the element region and a second end extending out of the substrate from a first side of the substrate, a plurality of control terminals disposed in a control region that is adjacent to a second side of the substrate opposite the first side, and a sealing member that seals the principal surface and the control region.

A signal transmission apparatus includes: a first lead frame; a second lead frame spaced from the first lead frame; a primary semiconductor chip electrically connected to the first lead frame; a secondary semiconductor chip electrically connected to the second lead frame; and a signal isolator through which a signal is isolatedly transmitted from the primary semiconductor chip to the secondary semiconductor chip, the signal isolator having a first main surface that is bonded to both the first lead frame and the second lead frame.

A packaged Radio Frequency power transistor device is described, which comprises a component carrier a die comprising a semiconductor transistor having a source, a gate and a drain, wherein the die is mounted at the component carrier, a ground connection being electrically connected to the source, an output lead being electrically connected to the drain, a resonance circuit being electrically inserted between the output lead and the ground connection, and a video lead being electrically connected to the resonance circuit. The video lead is configured for being connected to a first contact of a decoupling capacitor. The ground connection is configured for being connected to a second contact of the decoupling capacitor. It is further described a RF power amplifier comprising such a packaged Radio Frequency power transistor device.

A circuit board includes an insulating layer, a ground layer formed on a first surface of the insulating layer and including a plurality of openings arranged in first and second surface directions, each of the openings having a shape of a polygon having five or more sides, and a wiring layer formed on a second surface of the insulating layer opposite to the first surface.

A die interconnect system having a first die with a plurality of connection pads, and a ribbon lead extending from the first die, the ribbon lead having a plurality of metal cores with a core diameter, and a dielectric layer surrounding the metal core with a dielectric thickness, with at least a portion of dielectric being fused between adjacent metal cores along the length of the plurality of metal cores, and an outer metal layer attached to ground.

A noble metal-coated silver bonding wire for ball bonding wire includes a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes at least one palladium layer, the total palladium content relative to the entire wire is not less than 0.01 mass % and not more than 5.0 mass %, and the total sulfur group element content relative to the entire wire is not less than 0.1 mass ppm and not more than 100 mass ppm.

Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit chip which receives voltages of a drain electrode and a source electrode of the MOSFET and supplies a signal to a gate electrode to control the MOSFET on the basis of the voltage; a second external electrode which is disposed on an opposite side of the first external electrode with respect to the MOSFET chip and includes an external terminal on a center axis of the circular outer peripheral portion of the first external electrode; and an isolation substrate which isolates the control circuit chip from the external electrode. The first external electrode, the drain electrode and the source electrode of the MOSFET chip, and the second external electrode are disposed to be overlapped in a direction of the center axis. The drain electrode of the MOSFET chip and the first external electrode are connected. The source electrode of the MOSFET chip and the second external electrode are connected.

A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled to the wide bandgap semiconductor device, and a first electrode electrically coupled to the wide bandgap semiconductor device and positioned between the wide bandgap semiconductor device and the semiconductor cooling chip. The semiconductor cooling chip is positioned between a substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet port and the substrate outlet port and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more cooling chip fluid channels extending into the semiconductor cooling chip.

A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.