A power module is obtained in which the thermal resistance in the range from a semiconductor device to a base plate is reduced and the stress in the joining portion is relieved. The power module includes at least one semiconductor device, an insulating substrate having an insulating layer, a circuit layer provided on an upper surface of the insulating layer and a metal layer provided on a lower surface of the insulating layer, and a sintering joining member with an upper surface larger in outer circumference than a back surface of the at least one semiconductor device, to join together the back surface of the at least one semiconductor device and an upper surface of the circuit layer on an upper-surface side of the insulating layer.

A power semiconductor die includes a substrate and a drift layer on the substrate. The drift layer includes an active area, an edge termination area surrounding the active area, and a thermal dissipation area surrounding the edge termination area. The thermal dissipation area is configured to reduce a thermal resistance of the power semiconductor die. By providing the thermal dissipation area, the operating voltage and/or current of the power semiconductor die can be increased without an increase in the active area. Further, the manufacturing yield of the power semiconductor die can be improved.

A power semiconductor module includes: an electrically insulative frame having opposite first and second mounting sides, and a border that defines a periphery of the electrically insulative frame; a first substrate seated in the electrically insulative frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a plurality of busbars attached to the first substrate and extending through the border of the electrically insulative frame; a plurality of fixing positions at the first mounting side of the electrically insulative frame; and a plurality of electrically insulative protrusions jutting out from the second mounting side of the electrically insulative frame, wherein the protrusions are vertically aligned with the fixing positions. Methods of producing the power semiconductor module and power electronic assemblies that incorporate the power semiconductor module are also described.

A semiconductor module arrangement includes a housing and at least one pair of semiconductor substrates arranged inside the housing. Each pair of semiconductor substrates includes first and second semiconductor substrates. The first semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The second semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential, and the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential that is opposite to the first electrical potential.

A packaged electronic device includes first conductive leads and second conductive leads at least partially exposed to an exterior of a package structure, and a multilevel lamination structure in the package structure. The multilevel lamination structure includes a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit, a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit, and a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.

In a RC-IGBT chip, an anode electrode film and an emitter electrode film are arranged with a distance therebetween. The anode electrode film and the emitter electrode film are electrically connected by a wiring conductor having an external impedance and an external impedance. The external impedance and the external impedance include the resistance of the wiring conductor and the inductance of the wiring conductor.

A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.

An intelligent power module, which includes: a lead frame; a plurality of signal processing chips, disposed on the lead frame; at least one bridge die, configured to operably transmit signals among the signal processing chips; and a package structure, encapsulating the lead frame, the signal processing chips and the bridge die.

A Doherty amplifier includes a first amplifier that includes first output fingers and a first output electrode connected to the first output fingers, a second amplifier that includes second output fingers and a second output electrode connected to the second output fingers, a first bonding wire connected between a first region in the first output electrode and a second region in the second output electrode, a second bonding wire connected between a third region in the first output electrode and a fourth region in the second output electrode, and at least one of a first capacitor connected in series with the first bonding wire, and a second capacitor connected in parallel with the second bonding wire, wherein the first and the third regions are regions to which the first output fingers are connected, and the second and the fourth regions are regions to which second output fingers are connected.

An improved system for measuring current within a power semiconductor module is disclosed, where the system is integrated within the power module. The system includes a point field detector sensing a magnetic field resulting from current flowing in one phase of the module. A lead frame conductor may be provided to shape the magnetic field and minimize the influence of cross-coupled magnetic fields from currents conducted in other power semiconductor devices within one phase of the module. Optionally, a second point field detector may be provided at a second location within the module to sense a magnetic field resulting from the current flowing in the same phase of the module. Each phase of the power module includes at least one point field detector. A decoupling circuit is provided to decouple multiple currents flowing within the same phase or to decouple currents flowing within different phases of the power module.