Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

Various embodiments of a die carrier package and a method of forming such package are disclosed. The package includes one or more dies disposed within a cavity of a carrier substrate, where a first die contact of one or more of the dies is electrically connected to a first die pad disposed on a recessed surface of the cavity, and a second die contact of one or more of the dies is electrically connected to a second die pad also disposed on the recessed surface. The first and second die pads are electrically connected to first and second package contacts respectively. The first and second package contacts are disposed on a first major surface of the carrier substrate adjacent the cavity.

A semiconductor device includes: a supporting member having a wiring including a die-pad; a semiconductor element bonded to the die-pad; a wire bonded to the wiring and the semiconductor element; and a bonding layer that has a conductivity and bonds the die-pad and the semiconductor element. When viewed in a thickness direction of the semiconductor element, the die-pad includes a first region included inside a peripheral edge of the semiconductor element and a second region that is connected to the first region and extends farther then the peripheral edge of the semiconductor element. When viewed in the thickness direction, the wire is separated from the second region.

An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

A bonded structure includes a semiconductor element, an electrical conductor and a sintered metal layer. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a first direction and includes a reverse-surface electrode on the element reverse surface. The electrical conductor has a mount surface facing in a same direction as the element obverse surface and supports the semiconductor element with the mount surface facing the element reverse surface. The sintered metal layer bonds the semiconductor element to the electrical conductor and electrically connects the reverse-surface electrode and the electrical conductor. The mount surface includes a roughened area roughened by a roughening process. The sintered metal layer is formed on the roughened area.

A semiconductor device substrate assembly may include a first substrate, comprising: a first insulator plate; and a first patterned metal layer, disposed on the first insulator plate, wherein the first insulator plate comprises a first material and a first thickness. The assembly may include a second substrate, comprising: a second insulator plate; and a second patterned metal layer, disposed on the second insulator plate, wherein the second insulator plate comprises the first material and the first thickness. The assembly may also include a third substrate, disposed between the first substrate and the second substrate, comprising: a third insulator plate; and a third patterned metal layer, disposed on the third insulator plate, wherein the third insulator plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness differs from the first material and the first thickness, respectively.

A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices. The power module further including a base plate and a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module.

A semiconductor device substrate assembly may include a first substrate, comprising: a first insulator plate; and a first patterned metal layer, disposed on the first insulator plate, wherein the first insulator plate comprises a first material and a first thickness. The assembly may include a second substrate, comprising: a second insulator plate; and a second patterned metal layer, disposed on the second insulator plate, wherein the second insulator plate comprises the first material and the first thickness. The assembly may also include a third substrate, disposed between the first substrate and the second substrate, comprising: a third insulator plate; and a third patterned metal layer, disposed on the third insulator plate, wherein the third insulator plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness differs from the first material and the first thickness, respectively.

A semiconductor unit includes a plurality of semiconductor chips, and an insulated circuit board including an insulating plate having, in a plan view of the semiconductor unit, a rectangular shape surrounded by first and second sides opposite to each other and third and fourth sides perpendicular to the first and second sides and opposite to each other, an output circuit pattern and an input circuit pattern on a front surface of the insulating plate. The output and input circuit patterns each extend from the third side to the fourth side, and disposed in this order side by side in a main current direction that is a direction from the first side toward the second side. The plurality of semiconductor chips are bonded to the input circuit pattern at an area extending from the third side to the fourth side and including a center of the third and fourth sides.

According to the present disclosure, a bidirectional switch circuit includes a first semiconductor device including a first backside electrode electrically connected to a first pattern and a first upper surface electrode, a second semiconductor device including a second backside electrode electrically connected to a second pattern and a second upper surface electrode, a first diode including a first cathode electrode electrically connected to the first pattern and a first anode electrode, a second diode including a second cathode electrode electrically connected to the first pattern and a second anode electrode, first wiring electrically connecting the first upper surface electrode and the second anode electrode and second wiring electrically connecting the second upper surface electrode and the first anode electrode, wherein the first upper surface electrode, the second upper surface electrode, the first anode electrode and the second anode electrode are electrically connected to each other.