A semiconductor device forming a bidirectional switch includes first and second carriers, first and second semiconductor chips arranged on the first and second carriers, respectively, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor chips. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.

A light emitting device includes: a base having a bottom face and a lateral part surrounding the bottom face and extending upwards from the bottom face, wherein the lateral part comprises a first stepped portion and a second stepped portion facing the first stepped portion; a first semiconductor laser element disposed on the bottom face and located between the first stepped portion and the second stepped portion in a top view, wherein the first semiconductor laser element is configured to emit light towards the second stepped portion; a first wiring region located on the first stepped portion; and one or more first wires, each having a first end that is connected to the first wiring region. At least one of the one or more first wires is electrically connected to the first semiconductor laser element.

A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface.

The present invention provides a semiconductor device for reducing parasitic inductance. The semiconductor device of the present invention includes: a semiconductor chip, including a front surface and a hack surface, and including a source pad, a drain pad and a gate pad on the front surface; a die pad, disposed under the semiconductor chip and bonded to the hack surface of the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin, sealing the semiconductor chip, the die pad and each of the leads. At least one via for external connection is formed in the semiconductor chip to connect to the source pad, and the via for external connection is disposed on a circumferential portion of the semiconductor chip in perspective view.

A semiconductor element is mounted on a die pad, and electrode pads arranged along the outer circumference of an upper surface of the semiconductor element are electrically connected to leads by wires, respectively. The semiconductor element has an element region having a high sensitivity with respect to stress, and an element region having a relatively low sensitivity with respect to stress. A low-stress resin film is provided on the element region having a high sensitivity with respect to stress. The semiconductor element, the low-stress resin film, the die pad, and the leads are covered with an encapsulating resin.

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

A flow sensor includes a semiconductor, an electric control circuit, a lead frame, and a spacer. The spacer is disposed in a clearance between the lead frame and the semiconductor device on an opposite side from a joint portion of the semiconductor device with the lead frame on a side of the electric control circuit across the diaphragm disposed therebetween. A surface of the electric control circuit and a part of a surface of the semiconductor device is covered with resin while the air flow sensing unit is exposed. At the joint portion, the semiconductor device is attached to the lead frame via an adhesive.

A flow sensor includes a semiconductor, an electric control circuit, a lead frame, and a spacer. The spacer is disposed in a clearance between the lead frame and the semiconductor device on an opposite side from a joint portion of the semiconductor device with the lead frame on a side of the electric control circuit across the diaphragm disposed therebetween. A surface of the electric control circuit and a part of a surface of the semiconductor device is covered with resin while the air flow sensing unit is exposed. At the joint portion, the semiconductor device is attached to the lead frame via an adhesive.