A semiconductor package includes a package substrate, semiconductor chips stacked on the package substrate, and electrical connectors that connect internal circuitry of each of the chips to the package substrate. Each of the semiconductor chips includes a chip selection pad for transmitting a chip selection signal to the internal circuitry of the semiconductor chip and a chip dummy pad, electrically isolated from the internal circuitry, along a first side of the semiconductor chip. The electrical connectors include a lower chip connector that electrically connects the package substrate to the chip selection pad of the lower semiconductor chip, a first auxiliary connector that electrically connects the package substrate to the chip dummy pad of the lower semiconductor chip, and a second auxiliary connector that electrically connects the chip dummy pad of the lower semiconductor chip to the chip selection pad of the upper semiconductor chip.

An insulating gate semiconductor device includes an insulating gate semiconductor element, an insulating circuit board, and a main-current path member. A main-current of the insulating gate semiconductor element flows toward a first external terminal in the main-current path member; and a gate-current path member, being patterned so as to have a linearly extending portion arranged in parallel to a linearly extending portion of the main-current path member in a planar pattern on the insulating circuit board, being provided to connect between a second external terminal and a gate electrode of the insulating gate semiconductor element. A current which is induced in the gate-current path member by mutual induction caused by a change in magnetic field implemented by the main-current is used for increasing the gate-current in a turn-on period of the insulating gate semiconductor element.

a memory system may include: a memory device including a plurality of memory dies and suitable for performing, in the plurality of memory dies, command operations; and a controller suitable for: dividing sub-jobs of a command job corresponding to the command operations on a logical unit size basis; queuing the divided sub-jobs; and performing the queued sub-jobs to the memory dies with variable operating energy levels and operating clocks. The controller may monitor a status and a job load for at least one queued sub-job while performing the at least one queued sub-job to the memory dies, and interactively and dynamically adjusts an energy level and an operating clock for the at least one queued sub-job according to a result of the monitoring.

A semiconductor package includes a package substrate, semiconductor chips stacked on the package substrate, and electrical connectors that connect internal circuitry of each of the chips to the package substrate. Each of the semiconductor chips includes a chip selection pad for transmitting a chip selection signal to the internal circuitry of the semiconductor chip and a chip dummy pad, electrically isolated from the internal circuitry, along a first side of the semiconductor chip. The electrical connectors include a lower chip connector that electrically connects the package substrate to the chip selection pad of the lower semiconductor chip, a first auxiliary connector that electrically connects the package substrate to the chip dummy pad of the lower semiconductor chip, and a second auxiliary connector that electrically connects the chip dummy pad of the lower semiconductor chip to the chip selection pad of the upper semiconductor chip.

Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

A power module (1) comprising at least one substrate (2), at least one switching device (3) located on the substrate (2), at least one power path (6) for supplying power to the at least one switching device (3) and at least one auxiliary path (7, 10) for controlling and/or monitoring the switching device (3), wherein the at least one auxiliary path (7, 10) comprises at least one connection portion (9, 12, 17, 18, 19) that comprises two or more connectors (8, 11, 20) electrically connected in parallel. wherein the power module (1) comprises several switching devices (3) having corresponding auxiliary paths (7, 10), wherein at least one of the corresponding auxiliary paths (7, 10) comprises a connection portion (9, 12, 17, 18, 19) with parallel connectors (8, 11. 20) and wherein at least another one of the corresponding auxiliary paths (7, 10) comprises a connection portion (9, 12, 17, 18, 19) with parallel connectors (8, 11, 20) or comprises a connection portion (13) with a single connector, wherein the number of the connectors (8, 11, 20) is different in

A bi-directional switch that includes a first terminal, a second terminal, and a plurality of ballast circuits is provided. Each ballast circuit includes a first metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a first input connector, a first output connector, a first body, and a first body diode, and a second MOSFET comprising a second input connector, a second output connector, a second body, and a second body diode. Each first input connector is coupled to the first terminal, each second input connector is coupled to the second terminal, and each first output connector is coupled only to the second output connector of the second MOSFET that is in a same ballast circuit.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

Systems, methods, and devices related to techniques for reducing inter-die signal loads within a multi-die package are disclosed. The multi-die package includes a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communication with the first memory die via an inter-die connection. A technique involves adding an additional wirebond pad to each die in the multi-die package. When the inter-die connections are made, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. By not connecting to the transmitter of the second memory die, the first memory die transmits inter-die signals to the second memory die such that a lower signal load is achieved within the multi-die package.