The present application provides a semiconductor module and a power conversion device wherein wiring inductance is reduced. The semiconductor module is characterized by including a semiconductor element, a first terminal on which the semiconductor element is mounted, a second terminal disposed in a periphery of the semiconductor element and having a multiple of wiring portions, and a multiple of connection lines extending in multiple directions from an upper face of the semiconductor element and connected to each of the multiple of wiring portions of the second terminal, wherein a free region is provided among the multiple of wiring portions, and the multiple of connection lines and the multiple of wiring portions forming current paths with each of the multiple of connection lines are of the same potential.

Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.

Memory devices are disclosed. A memory device may include a command and address (CA) interface region including a first CA input circuit configured to generate a first CA output AND a second CA input circuit configured to generate a second CA output. The first CA input circuit and the second CA input circuit are arranged in a mirror relationship. The CA interface region further includes a swap circuit configured to select one of the first CA output and the second CA output for a first internal CA signal and select the other of the first CA output and the second CA output for a second internal CA signal. Memory systems and systems are also disclosed.

A semiconductor device includes a semiconductor chip, a bonding member, and a planar laminated substrate having the semiconductor chip bonded to a front surface thereof via the bonding member. The laminated substrate includes a planar ceramic board, a high-potential metal layer, a low-potential metal layer, an intermediate layer. The planar ceramic board contains a plurality of ceramic particles. The high-potential metal layer contains copper and is bonded to a first main surface of the ceramic board. The low-potential metal layer contains copper, is bonded to a second main surface of the ceramic board, and has a potential lower than a potential of the first main surface of the high-potential metal layer. The intermediate layer is provided between the second main surface and the low-potential metal layer and includes a first oxide that contains at least either magnesium or manganese.

In an optical receiver circuit which suppresses an unnecessary increase in impedance and occurrences of resonance and radiation noise and which produces preferable high-frequency transmission characteristics, a PD submount mounted with a PD chip and a chip capacitor and a TIA carrier mounted with a TIA chip are electrically connected to each other by a bonding wire. The chip includes an anode electrode pad and a cathode electrode pad, anode electrode-side ground pads are formed at positions that sandwich the pad, and cathode electrode-side ground pads are formed at positions that sandwich the pad. A wire electrically connects the pad and a signal pad for input of the chip to each other, a wire electrically connects the pad and the capacitor to each other, and a wire electrically connects the pads and the pads to each other.

Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

Isolators for signals and/or powers transmitted between two circuits configured to operate at different voltage domains are provided. The isolators may have working voltages, for example, higher than 500 Vrms, higher than 1000 Vrms, or between 333 Vrms and 1800 Vrms. The isolators may have a fully symmetrical configuration. The isolators may include a primary winding coupled to a driver and a secondary winding coupled to a receiver. The primary and secondary windings may be laterally coupled to and galvanically isolated from each other. The primary and secondary windings may include concentric traces. The primary and secondary windings may be fabricated using a single metallization layer on a substrate.

A light emitting device includes: a base having a first stepped portion and a second stepped portion; a light emitting element; an electronic member configured to be irradiated by light emitted from the light emitting element; a first wiring region located on the first stepped portion; a second wiring region located on the second stepped portion; wires connected to the light emitting element and the electronic member. The wires includes a first and second wires. The first wire has a first end that is connected to the first wiring region, and a second end. The second wire has a first end that is connected to the second wiring region, and a second end. A position of the second end of the first wire relative to the bottom face is lower than a position of the second end of the second wire relative to the bottom face.

A sensor package structure is provided and includes a substrate, a sensor chip, a ring-shaped supporting layer, and a light-permeable sheet. The sensor chip is disposed on and electrically coupled to the substrate. The ring-shaped supporting layer is disposed on the sensor chip and surrounds a sensing region of the sensor chip. The light-permeable sheet has a ring-shaped notch recessed in a peripheral edge of an inner surface of the light-permeable sheet, and a depth of the ring-shaped notch with respect to the inner surface is at least 10 tim. The light-permeable sheet is disposed on the ring-shaped supporting layer through the ring-shaped notch, and the inner surface is not in contact with the ring-shaped supporting layer, so that the inner surface of the light-permeable sheet, an inner side of the ring-shaped supporting layer, and the top surface of the sensor chip jointly define an enclosed space.