A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.

A deteriorated section identifying unit refers to correspondence information that defines a deteriorated section of a plurality of bonding sections to the emitter electrode surface to which the first bonding wires are connected, for a combination of temporal change of a first voltage that is a difference between a potential at a collector main terminal and a potential at the emitter main terminal and temporal change of a second voltage that is a difference between a potential at the emitter reference terminal and a potential at the emitter main terminal, and identifies the deteriorated section corresponding to a combination of temporal change of the first voltage measured by a first voltage measuring circuit and temporal change of the second voltage measured by a second voltage measuring circuit.

A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.

A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k−1th semiconductor chip when k is 1.

A semiconductor device is disclosed including a wire bonded die stack where the bond wires skip dies in the die stack to provide bond wires having a long length. In one example, the semiconductor dies are stacked on top of each other with offsets along two orthogonal axes so that the dies include odd numbered dies interspersed and staggered with respect to even numbered dies only one of the axes. Wire bonds may be formed between the odd numbered dies, skipping the even numbered dies, and wire bonds may be formed between the even numbered dies, skipping the odd numbered dies. The long length of the bond wires increases an inductance of the wire bonds relative to parasitic capacitance of the semiconductor dies, thereby increasing signal path bandwidth of the semiconductor device.

A semiconductor device includes a support member, a first switching element, a second switching element, a first passive element, a second passive element, and an electrical conductor. The support member includes a plurality of wiring parts, and the plurality of wiring parts include a first wiring section and a second wiring section spaced apart from each other in a first direction perpendicular to the thickness direction of the support member. The first switching element is electrically connected to the first wiring section. The second switching element is electrically connected to the first switching element and the second wiring section. The first passive element has a first electrode and a second electrode, and the first electrode is bonded to the first wiring section. The second passive element has a third electrode and a fourth electrode, and the fourth electrode is bonded to the second wiring section. The electrical conductor connects the second electrode and the third electrode to each other. At least one of the first passive element and the second passive element is a capacitor.

A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.

The present disclosure relates to the field of display technologies and, in particular to a display panel and a display device. The display panel includes a circuit board assembly, a plurality of sub-pixels, a base substrate, and a plurality of connecting wires. The circuit board assembly includes a plurality of first bonding pads; a plurality of second bonding pads are disposed in the non-display area of the base substrate; the plurality of connecting wires connect the plurality of first bonding pads and the plurality of second bonding pads. Adjacent connecting wires have different maximum stretchable heights in a direction perpendicular to the base substrate.

Provided is a semiconductor apparatus comprising: a semiconductor substrate; an element electrode provided above the semiconductor substrate; an element electrode pad electrically connected to the element electrode; and a wire configured to connect to the element electrode pad at a plurality of connection points, wherein the semiconductor substrate includes an emitter region of a first conductivity type arrayed in an array direction, the emitter region facing the element electrode on an upper surface of the semiconductor substrate, wherein a density of the emitter region below a connection point of any of the wires is different from a density of the emitter region below a connection point of any other of the wires.

A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.