Patent classifications
H01L2224/49433
POWER MODULE
A power module includes a substrate that is electrically insulative and includes a substrate main surface and a substrate back surface at opposite sides in a thickness direction. The power module also includes a mounting layer that is conductive and arranged on the substrate main surface. The power module further includes a graphite plate having anisotropic thermal conductivity and including a plate main surface and a plate back surface at opposite sides in the thickness direction. The plate back surface is connected to the mounting layer. The power module further includes a power semiconductor element arranged on the plate main surface.
POWER MODULE
A power module includes a housing having a carrier plate, housing walls and a housing cover. Semiconductor elements and a temperature sensor unit having a temperature sensor are disposed in the interior of the housing on the carrier plate. Partitions disposed in the interior of the housing separate the temperature sensor unit from the semiconductor elements and enclose the temperature sensor unit in a chamber.
Electrical interface for printed circuit board, package and die
A circuit board and package assembly electrically connecting a die to a circuit board. The circuit board has signal paths terminating in a signal pad located on an insulating layer. The circuit board also includes a ground pad on the insulating layer that has a concave shaped side forming a recess, the with a signal pad at least partially within the recess. A package has package ground pads aligned with the circuit board ground pads and package signal pads aligned with circuit board signal pads. The package ground pads extend through the package to connect to package ground paths, which extend toward the die. The package signal pads extend through the package to connect to package signal paths and the package signal paths extend toward the die, maintaining a consistent distance from the package ground paths. Multiple-tier bond wires connect the package bond locations to the die bond pads.
Method of producing a semiconductor package
A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.
Method of producing a semiconductor package
A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.
SEMICONDUCTOR POWER MODULE
A semiconductor power module including an insulating substrate having one surface and another surface, an output side terminal arranged at a one surface side of the insulating substrate, a first power supply terminal arranged at the one surface side of the insulating substrate, a second power supply terminal to which a voltage of a magnitude different from a voltage applied to the first power supply terminal is to be applied, and arranged at an other surface side of the insulating substrate so as to face the first power supply terminal across the insulating substrate, a first switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the first power supply terminal, and a second switching device arranged at the one surface side of the insulating substrate and electrically connected to the output side terminal and the second power supply terminal.
Integrated circuit (IC) package with stacked die wire bond connections, and related methods
An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.
Semiconductor device
A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.
Multi-row QFN semiconductor package
A semiconductor package includes at least one die attach pad of a leadframe, at least one semiconductor die mounted on the at least one die attach pad; and a plurality of lead terminals disposed around the at least one die attach pad and electrically connected to respective input/output (I/O) pads on the at least one semiconductor die through a plurality of bond wires. The plurality of lead terminals comprises first lead terminals, second lead terminals, and third lead terminals, which are arranged in triple row configuration along at least one side of the semiconductor package. Each of the first lead terminals, second lead terminals, and third lead terminals has an exposed base metal on a cut end thereof.
Multi-row QFN semiconductor package
A semiconductor package includes at least one die attach pad of a leadframe, at least one semiconductor die mounted on the at least one die attach pad; and a plurality of lead terminals disposed around the at least one die attach pad and electrically connected to respective input/output (I/O) pads on the at least one semiconductor die through a plurality of bond wires. The plurality of lead terminals comprises first lead terminals, second lead terminals, and third lead terminals, which are arranged in triple row configuration along at least one side of the semiconductor package. Each of the first lead terminals, second lead terminals, and third lead terminals has an exposed base metal on a cut end thereof.