A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

An electronic device includes a substrate, an electronic component, a first interposing layer and a second interposing layer. The substrate is non-planar and the substrate includes a first substrate pad and a second substrate pad. The electronic component includes a first component pad and a second component pad corresponding to the first substrate pad and the second substrate pad respectively. When the first component pad contacts the first substrate pad, a height difference exists between the second component pad and the second substrate pad. The first interposing layer connects between the first component pad and the first substrate pad. The second interposing layer connects between the second component pad and the second substrate pad. A thickness difference between the first interposing layer and the second interposing layer is 0.5 to 1 time the height difference.

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.

A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.