A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.

A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm.sup.3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm.sup.3.

A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm.sup.3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm.sup.3.

A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.

A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.