A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and an electronic component disposed on the substrate, and the first package component is mounted to the substrate. The package structure further includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot, the first foot and the second foot extend toward the substrate, the electronic component is covered by the ring structure and located between the first foot and the second foot, and the first package component is exposed from the ring structure.

A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and an electronic component disposed on the substrate, and the first package component is mounted to the substrate. The package structure further includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot, the first foot and the second foot extend toward the substrate, the electronic component is covered by the ring structure and located between the first foot and the second foot, and the first package component is exposed from the ring structure.

The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.

The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.

A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

A semiconductor package including a passivation film, a mold layer on the passivation film, a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion, the first portion penetrating the passivation film, the second portion penetrating a part of the mold layer, a solder ball on the first portion of the connecting pad, an element on the second portion of the connecting pad, a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern inside the insulating layer, and a semiconductor chip on the wiring structure may be provided.

A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved.

A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved.

A semiconductor package includes a redistribution structure having a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface. A semiconductor chip is on the first surface of the redistribution structure and is electrically connected to the redistribution layer. An encapsulant is on at least a portion of the semiconductor chip. A passive element is on the second surface of the redistribution structure. The passive element includes a connection surface facing the second surface, a connection terminal on the connection surface, a non-connection surface opposite to the connection surface, and a side surface extending from the connection surface to the non-connection surface. A connection bump is adjacent the passive element on the second surface and is electrically connected to the redistribution layer. A sealing material is on at least a portion of the connection surface, the non-connection surface, and the side surface of the passive element.