A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

A package structure and a method of forming the same are provided. The package structure includes a package substrate and an interposer substrate over the package substrate. The interposer substrate has a first surface facing the package substrate and a second surface opposite the first surface. A first semiconductor device is disposed on the first surface, and a second semiconductor device is disposed on the second surface. Conductive structures are disposed between the interposer substrate and the package substrate. The first semiconductor device is located between the conductive structures. A first side of the first semiconductor device is at a first distance from the most adjacent conductive structure, and a second side of the first semiconductor device is at a second distance from the most adjacent conductive structure. The first side is opposite the second side, and the first distance is greater than the second distance.

A package structure and a method of forming the same are provided. The package structure includes a package substrate and an interposer substrate over the package substrate. The interposer substrate has a first surface facing the package substrate and a second surface opposite the first surface. A first semiconductor device is disposed on the first surface, and a second semiconductor device is disposed on the second surface. Conductive structures are disposed between the interposer substrate and the package substrate. The first semiconductor device is located between the conductive structures. A first side of the first semiconductor device is at a first distance from the most adjacent conductive structure, and a second side of the first semiconductor device is at a second distance from the most adjacent conductive structure. The first side is opposite the second side, and the first distance is greater than the second distance.

A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip over the package substrate, and at least one integrated device integrated with the semiconductor chip. The integrated device is integrated directly beneath the semiconductor chip in order to facilitate signal transmission. Consequently, the signal integrity and the power integrity of the package structure are improved. In addition, the integrated device does not take up installation space over the package substrate, so the size of the package substrate and of the overall package structure can also be reduced.

A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip over the package substrate, and at least one integrated device integrated with the semiconductor chip. The integrated device is integrated directly beneath the semiconductor chip in order to facilitate signal transmission. Consequently, the signal integrity and the power integrity of the package structure are improved. In addition, the integrated device does not take up installation space over the package substrate, so the size of the package substrate and of the overall package structure can also be reduced.

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

A semiconductor package includes a lower semiconductor chip disposed on a substrate, at least one upper semiconductor chip disposed on the lower semiconductor chip, a heat spreader bonded on the lower semiconductor chip and the at least one upper semiconductor chip, and an encapsulant surrounding side surfaces of the heat spreader. A lower surface of the heat spreader includes a first protrusion and a non-protruding portion, the first protrusion is in contact with an upper surface of the lower semiconductor chip, and the non-protruding portion is in contact with an upper surface of the at least one upper semiconductor chip.

A semiconductor package includes a lower semiconductor chip disposed on a substrate, at least one upper semiconductor chip disposed on the lower semiconductor chip, a heat spreader bonded on the lower semiconductor chip and the at least one upper semiconductor chip, and an encapsulant surrounding side surfaces of the heat spreader. A lower surface of the heat spreader includes a first protrusion and a non-protruding portion, the first protrusion is in contact with an upper surface of the lower semiconductor chip, and the non-protruding portion is in contact with an upper surface of the at least one upper semiconductor chip.

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

A semiconductor device and a semiconductor package including the same are provided. The semiconductor device includes a semiconductor element; a protective layer disposed adjacent to the surface of the semiconductor element, the protective layer defining an opening to expose the semiconductor element; a first bump disposed on the semiconductor element; and a second bump disposed onto the surface of the protective layer. The first bump has a larger cross-section surface area than the second bump.