A semiconductor module having a first metal wiring board, a second metal wiring board, a third metal wiring board, and a first semiconductor element and a second semiconductor element that each include an emitter electrode and a collector electrode. The second metal wiring board is disposed over a principal surface of the first metal wiring board with an insulation material therebetween. The third metal wiring board has a principal surface thereof facing the first metal wiring board. The first and second semiconductor elements are disposed to face directions opposite to each other. The collector electrodes of the first and second semiconductor elements respectively face the principal surfaces of the first and third metal wiring boards. The emitter electrodes of the first and second semiconductor elements are respectively connected to the principal surfaces of the third and second metal wiring boards.

A semiconductor module having a first metal wiring board, a second metal wiring board, a third metal wiring board, and a first semiconductor element and a second semiconductor element that each include an emitter electrode and a collector electrode. The second metal wiring board is disposed over a principal surface of the first metal wiring board with an insulation material therebetween. The third metal wiring board has a principal surface thereof facing the first metal wiring board. The first and second semiconductor elements are disposed to face directions opposite to each other. The collector electrodes of the first and second semiconductor elements respectively face the principal surfaces of the first and third metal wiring boards. The emitter electrodes of the first and second semiconductor elements are respectively connected to the principal surfaces of the third and second metal wiring boards.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die.

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die.

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.