A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and an electronic component disposed on the substrate, and the first package component is mounted to the substrate. The package structure further includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot, the first foot and the second foot extend toward the substrate, the electronic component is covered by the ring structure and located between the first foot and the second foot, and the first package component is exposed from the ring structure.

A semiconductor package including a passivation film, a mold layer on the passivation film, a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion, the first portion penetrating the passivation film, the second portion penetrating a part of the mold layer, a solder ball on the first portion of the connecting pad, an element on the second portion of the connecting pad, a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern inside the insulating layer, and a semiconductor chip on the wiring structure may be provided.

A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.

A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.

A manufacturing method of an electronic apparatus is provided, and the manufacturing method includes following steps. A substrate is provided. A plurality of first bonding pads are formed on the substrate. A plurality of electronic devices are provided, and each of the electronic devices includes at least one second bonding pad. The second bonding pads of the electronic devices corresponding to the first bonding pads are laminated onto the corresponding first bonding pads on the substrate, so as to bond the electronic devices to the substrate. The corresponding first and second bonding pads respectively have bonding surfaces with different surface topographies. The manufacturing method of the electronic apparatus is capable of reducing short circuit during a bonding process or improving a bonding yield.

A manufacturing method of an electronic apparatus is provided, and the manufacturing method includes following steps. A substrate is provided. A plurality of first bonding pads are formed on the substrate. A plurality of electronic devices are provided, and each of the electronic devices includes at least one second bonding pad. The second bonding pads of the electronic devices corresponding to the first bonding pads are laminated onto the corresponding first bonding pads on the substrate, so as to bond the electronic devices to the substrate. The corresponding first and second bonding pads respectively have bonding surfaces with different surface topographies. The manufacturing method of the electronic apparatus is capable of reducing short circuit during a bonding process or improving a bonding yield.

A semiconductor package includes a redistribution structure having a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface. A semiconductor chip is on the first surface of the redistribution structure and is electrically connected to the redistribution layer. An encapsulant is on at least a portion of the semiconductor chip. A passive element is on the second surface of the redistribution structure. The passive element includes a connection surface facing the second surface, a connection terminal on the connection surface, a non-connection surface opposite to the connection surface, and a side surface extending from the connection surface to the non-connection surface. A connection bump is adjacent the passive element on the second surface and is electrically connected to the redistribution layer. A sealing material is on at least a portion of the connection surface, the non-connection surface, and the side surface of the passive element.

A semiconductor structure includes: a substrate; a first dielectric layer over the substrate; a waveguide over the first dielectric layer; a second dielectric layer over the first dielectric layer and laterally surrounding the waveguide; a first conductive member and a second conductive member over the second dielectric layer and the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; a conductive bump on one side of the substrate and electrically connected to the first conductive member or the second conductive member; and a conductive via extending through the substrate and electrically connecting the conductive bump to the first conductive member or the second conductive member. The waveguide is configured to transmit an electromagnetic signal between the first conductive member and the second conductive member.

A semiconductor structure includes: a substrate; a first dielectric layer over the substrate; a waveguide over the first dielectric layer; a second dielectric layer over the first dielectric layer and laterally surrounding the waveguide; a first conductive member and a second conductive member over the second dielectric layer and the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; a conductive bump on one side of the substrate and electrically connected to the first conductive member or the second conductive member; and a conductive via extending through the substrate and electrically connecting the conductive bump to the first conductive member or the second conductive member. The waveguide is configured to transmit an electromagnetic signal between the first conductive member and the second conductive member.

A transfer method includes providing a first light emitting diode on a first substrate, performing a partial laser liftoff of the first light emitting diode from the first substrate, laser bonding the first light emitting diode to the backplane after performing the partial laser liftoff, and separating the first substrate from the first light emitting diode after the laser bonding.