A method of manufacturing a multi-layer wafer is provided. Under bump metallization (UMB) pads are created on each of two heterogeneous wafers. A conductive means is applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The stress compensating polymer layer has a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition.

In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

A semiconductor device has a leadframe and a first electrical component including a first surface disposed on the leadframe. A first clip bond is disposed over a second surface of the first electrical component. The first clip bond extends vertically through the semiconductor device. The first clip bond has a vertical member, horizontal member connected to the vertical member, die contact integrated with the horizontal member, and clip foot extending from the vertical member. A second electrical component has a first surface disposed on the first clip bond. A second clip bond is disposed over a second surface of the second electrical component opposite the first surface of the second electrical component. An encapsulant is deposited around the first electrical component and first clip bond. A second electrical component is disposed over the encapsulant. The clip foot is exposed from the encapsulant.

A semiconductor device has a leadframe and a first electrical component including a first surface disposed on the leadframe. A first clip bond is disposed over a second surface of the first electrical component. The first clip bond extends vertically through the semiconductor device. The first clip bond has a vertical member, horizontal member connected to the vertical member, die contact integrated with the horizontal member, and clip foot extending from the vertical member. A second electrical component has a first surface disposed on the first clip bond. A second clip bond is disposed over a second surface of the second electrical component opposite the first surface of the second electrical component. An encapsulant is deposited around the first electrical component and first clip bond. A second electrical component is disposed over the encapsulant. The clip foot is exposed from the encapsulant.

A microelectronic component comprises a substrate having at least one bond pad on a surface thereof and a metal pillar structure on the at least one bond pad, the metal pillar structure comprising a metal pillar on the at least one bond pad and a solder material having a portion within a reservoir within the metal pillar and another portion protruding from an end of the metal pillar opposite the at least one bond pad. Methods for forming the metal pillar structures, metal pillar structures, assemblies and systems incorporating the metal pillar structures are also disclosed.

A microelectronic component comprises a substrate having at least one bond pad on a surface thereof and a metal pillar structure on the at least one bond pad, the metal pillar structure comprising a metal pillar on the at least one bond pad and a solder material having a portion within a reservoir within the metal pillar and another portion protruding from an end of the metal pillar opposite the at least one bond pad. Methods for forming the metal pillar structures, metal pillar structures, assemblies and systems incorporating the metal pillar structures are also disclosed.

A semiconductor device includes a semiconductor substrate configured to include a first electrode layer, and a first barrier layer provided on the first electrode layer and bonded to a metal layer, and a circuit substrate configured to include a second electrode layer, and a second barrier layer provided on the second electrode layer and bonded to the metal layer, wherein the semiconductor substrate including a semiconductor element, and the circuit substrate are bonded via the metal layer containing Sn, a linear expansion coefficient of the first barrier layer is larger than that of the circuit substrate, and a linear expansion coefficient of the second barrier layer is smaller than that of the circuit substrate.

A semiconductor device includes a semiconductor substrate configured to include a first electrode layer, and a first barrier layer provided on the first electrode layer and bonded to a metal layer, and a circuit substrate configured to include a second electrode layer, and a second barrier layer provided on the second electrode layer and bonded to the metal layer, wherein the semiconductor substrate including a semiconductor element, and the circuit substrate are bonded via the metal layer containing Sn, a linear expansion coefficient of the first barrier layer is larger than that of the circuit substrate, and a linear expansion coefficient of the second barrier layer is smaller than that of the circuit substrate.

A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.