A method of manufacturing a semiconductor package includes forming a plurality of trenches at a first surface of a silicon substrate, forming a conductive pad inside each of the plurality of trenches, forming a redistribution layer on the first surface of the silicon substrate, forming an external connection terminal on a first surface of the redistribution layer, removing the silicon substrate to expose each conductive pad, mounting a semiconductor chip to be connected to the conductive pads, and forming an encapsulant to cover at least one surface of the semiconductor chip.

An organic light-emitting diode (OLED) display and a method of manufacturing an OLED display are disclosed. In one aspect, the method includes forming a data electrode layer and patterning the data electrode layer so as to form a source electrode, a drain electrode, and a pad electrode. The method can also include forming a first organic insulating layer over the source, drain and pad electrodes and forming a via hole corresponding to the source electrode or the drain electrode in the first organic insulating layer via a one tone mask. The method can further include forming an OLED including an anode electrically connected to the source electrode or the drain electrode, an organic emission layer, and a cathode, and etching a first portion of the first organic insulating layer formed over the pad electrode and a second portion of the organic emission layer formed over the pad electrode.

An organic light-emitting diode (OLED) display and a method of manufacturing an OLED display are disclosed. In one aspect, the method includes forming a data electrode layer and patterning the data electrode layer so as to form a source electrode, a drain electrode, and a pad electrode. The method can also include forming a first organic insulating layer over the source, drain and pad electrodes and forming a via hole corresponding to the source electrode or the drain electrode in the first organic insulating layer via a one tone mask. The method can further include forming an OLED including an anode electrically connected to the source electrode or the drain electrode, an organic emission layer, and a cathode, and etching a first portion of the first organic insulating layer formed over the pad electrode and a second portion of the organic emission layer formed over the pad electrode.

Embodiments of three-dimensional (3D) memory devices with stacked device chips using interposers and fabrication methods thereof are disclosed. In an example, a 3D memory device includes first and second device chips and an interposer therebetween. The first device chip includes a peripheral device and a first chip contact on a surface of the first device chip and electrically connected to the peripheral device. The second device chip includes an alternating conductor/dielectric stack, a memory string extending vertically through the alternating conductor/dielectric stack, and a second chip contact on a surface of the second device chip and electrically connected to the memory string. The interposer includes an interposer substrate, first and second interposer contacts on opposite surfaces of the interposer and electrically connected to one another through the interposer substrate. The first and second interposer contacts are attached to the first and second chip contacts, respectively.

Embodiments of three-dimensional (3D) memory devices with stacked device chips using interposers and fabrication methods thereof are disclosed. In an example, a 3D memory device includes first and second device chips and an interposer therebetween. The first device chip includes a peripheral device and a first chip contact on a surface of the first device chip and electrically connected to the peripheral device. The second device chip includes an alternating conductor/dielectric stack, a memory string extending vertically through the alternating conductor/dielectric stack, and a second chip contact on a surface of the second device chip and electrically connected to the memory string. The interposer includes an interposer substrate, first and second interposer contacts on opposite surfaces of the interposer and electrically connected to one another through the interposer substrate. The first and second interposer contacts are attached to the first and second chip contacts, respectively.

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

A detection structure and a detection method are provided. The method includes the following. A display backplane, a detection circuit board, and a detection light-emitting diode (LED) chip are provided. The detection circuit board is disposed on the display backplane, to connect a first detection line on the detection circuit board with a first contact electrode and connect a second detection line on the detection circuit board with a second contact electrode. A drive signal is output via the display backplane to the first detection line and the second detection line. A contact electrode pair on the display backplane corresponding to the detection LED chip is determined to be abnormal on condition that the detection LED chip is unlighted.

A detection structure and a detection method are provided. The method includes the following. A display backplane, a detection circuit board, and a detection light-emitting diode (LED) chip are provided. The detection circuit board is disposed on the display backplane, to connect a first detection line on the detection circuit board with a first contact electrode and connect a second detection line on the detection circuit board with a second contact electrode. A drive signal is output via the display backplane to the first detection line and the second detection line. A contact electrode pair on the display backplane corresponding to the detection LED chip is determined to be abnormal on condition that the detection LED chip is unlighted.

An adhesive member includes: a conductive particle layer including a plurality of conductive particles; a non-conductive layer disposed on the conductive particle layer; and a screening layer interposed between the conductive particle layer and the non-conductive layer and includes a plurality of screening members spaced apart from each other.