A microelectronic wireless transmission device including: a substrate able to be traversed by radio waves intended to be emitted by the device, an antenna, an electrical power supply, an integrated circuit, electrically connected to the antenna and to the electrical power supply, and able to transmit to the antenna electrical signals intended to be emitted by the antenna in the form of the said radio waves, a cap rigidly connected to the substrate and forming, with the substrate, at least one cavity in which the antenna and the integrated circuit are positioned, where the cap comprises an electrically conductive material connected electrically to an electrical potential of the electrical power supply and/or of the integrated circuit, and able to form a reflector with regard to the radio waves intended to be emitted by the antenna.

Embodiments of the present invention provide an improved method and structure for flip chip implementation. The interconnections between the electronic circuit (e.g. silicon die) and the circuit board substrate are comprised of a metal alloy that becomes liquid at the operating temperature of the chip. This allows a softer underfill to be used, which in turn reduces stresses during operation and thermal cycling that are caused by the different coefficient of thermal expansion (CTE) of the electronic circuit chip and the circuit board substrate.

Embodiments of the present invention provide an improved method and structure for flip chip implementation. The interconnections between the electronic circuit (e.g. silicon die) and the circuit board substrate are comprised of a metal alloy that becomes liquid at the operating temperature of the chip. This allows a softer underfill to be used, which in turn reduces stresses during operation and thermal cycling that are caused by the different coefficient of thermal expansion (CTE) of the electronic circuit chip and the circuit board substrate.

A semiconductor device and a method of manufacturing a semiconductor device. For example, various aspects of this disclosure provide a semiconductor device having an ultra-thin substrate, and a method of manufacturing a semiconductor device having an ultra-thin substrate. As a non-limiting example, a substrate structure comprising a carrier, an adhesive layer formed on the carrier, and an ultra-thin substrate formed on the adhesive layer may be received and/or formed, components may then be mounted to the ultra-thin substrate and encapsulated, and the carrier and adhesive layer may then be removed.

A semiconductor device and a method of manufacturing a semiconductor device. For example, various aspects of this disclosure provide a semiconductor device having an ultra-thin substrate, and a method of manufacturing a semiconductor device having an ultra-thin substrate. As a non-limiting example, a substrate structure comprising a carrier, an adhesive layer formed on the carrier, and an ultra-thin substrate formed on the adhesive layer may be received and/or formed, components may then be mounted to the ultra-thin substrate and encapsulated, and the carrier and adhesive layer may then be removed.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.