The invention relates to a chip arrangement (10) and to a method for forming a contact connection (11) between a chip (18), in particular a power transistor or the like, and a conductor material track (14), the conductor material track being formed on a non-conductive substrate (12), the chip being arranged on the substrate or on a conductor material track (15), a silver paste (29) or a copper paste being applied to each of a chip contact surface (25) of the chip and the conductor material track (28), a contact conductor (30) being immersed into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, a solvent contained in the silver paste or the copper paste being at least partially vaporized by heating and the contact connection being formed by sintering the silver paste or the copper paste by means of laser energy.

The invention relates to a chip arrangement (10) and to a method for forming a contact connection (11) between a chip (18), in particular a power transistor or the like, and a conductor material track (14), the conductor material track being formed on a non-conductive substrate (12), the chip being arranged on the substrate or on a conductor material track (15), a silver paste (29) or a copper paste being applied to each of a chip contact surface (25) of the chip and the conductor material track (28), a contact conductor (30) being immersed into the silver paste or the copper paste on the chip contact surface and into the silver paste or the copper paste on the conductor material track, a solvent contained in the silver paste or the copper paste being at least partially vaporized by heating and the contact connection being formed by sintering the silver paste or the copper paste by means of laser energy.

A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

To provide a semiconductor module that has high reliability of electric connection by a solder and is inexpensive. A joint surface of an electrode jointing portion that is opposed to a surface to be jointed of a gate electrode of a bare-chip FET and a joint surface of a substrate jointing portion that is opposed to a surface to be jointed of another wiring pattern include an outgas releasing mechanism that makes outgas generated from a molten solder during solder jointing of a metal plate connector be released from solders interposed between the joint surfaces and the surfaces to be jointed.

To provide a semiconductor module that has high reliability of electric connection by a solder and is inexpensive. A joint surface of an electrode jointing portion that is opposed to a surface to be jointed of a gate electrode of a bare-chip FET and a joint surface of a substrate jointing portion that is opposed to a surface to be jointed of another wiring pattern include an outgas releasing mechanism that makes outgas generated from a molten solder during solder jointing of a metal plate connector be released from solders interposed between the joint surfaces and the surfaces to be jointed.

In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module.

In one implementation, a method of fabricating a power semiconductor package is disclosed. The method includes providing a conductive carrier array including a plurality of power modules held together with connecting bars, where each of the plurality of power modules includes a control transistor, a sync transistor, and a driver IC. The method further includes overlying on the conductive carrier array a heat spreader array including a plurality of power electrode heat spreaders such that each of the plurality of power electrode heat spreaders couples a drain of the sync transistor to a source of the control transistor in each power module.

To provide a semiconductor module capable of shortening of the manufacturing tact time, reducing the manufacturing costs, and improving assembility. A semiconductor module (30) includes substrate (31) made of metal, an insulating layer (32) formed on the substrate (31), a plurality of wiring patterns (33a to 33d) formed on the insulating layer (32), a bare-chip transistor (35) mounted on a wiring pattern (33a) via a solder (34a); and a metal plate connector (36a, 36b) jointing an electrode (S, G) of the bare-chip transistor (35) and a wiring pattern (33b, 33c) via a solder (34b, 34c). The metal plate connector (36a, 36b) has a bridge shape, and has a flat surface and a center of gravity at a middle portion of the component.

To provide a semiconductor module capable of shortening of the manufacturing tact time, reducing the manufacturing costs, and improving assembility. A semiconductor module (30) includes substrate (31) made of metal, an insulating layer (32) formed on the substrate (31), a plurality of wiring patterns (33a to 33d) formed on the insulating layer (32), a bare-chip transistor (35) mounted on a wiring pattern (33a) via a solder (34a); and a metal plate connector (36a, 36b) jointing an electrode (S, G) of the bare-chip transistor (35) and a wiring pattern (33b, 33c) via a solder (34b, 34c). The metal plate connector (36a, 36b) has a bridge shape, and has a flat surface and a center of gravity at a middle portion of the component.