A semiconductor device has a leadframe and a first electrical component disposed over the leadframe. A clip bond is disposed over the first electrical component. The clip bond has a plurality of recesses each having a different depth. A first recess is proximate to a first distal end of the first electrical component, and a second recess is proximate to a second distal end of the first electrical component opposite the first distal end of the first electrical component. A depth of the first recess is different from a depth of the second recess. A third recess is over a surface of the first electrical component. A depth of the third recess is different from the depth of the first recess and the depth of the second recess. A second electrical component is disposed over the leadframe. The clip bond extends over the second electrical component.

A semiconductor device has a leadframe and a first electrical component disposed over the leadframe. A clip bond is disposed over the first electrical component. The clip bond has a plurality of recesses each having a different depth. A first recess is proximate to a first distal end of the first electrical component, and a second recess is proximate to a second distal end of the first electrical component opposite the first distal end of the first electrical component. A depth of the first recess is different from a depth of the second recess. A third recess is over a surface of the first electrical component. A depth of the third recess is different from the depth of the first recess and the depth of the second recess. A second electrical component is disposed over the leadframe. The clip bond extends over the second electrical component.

An integrated circuit package includes a leadframe with a die pad and a lead. A semiconductor die is attached to a top surface of the die pad. A clip has a lead contact area with a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. A portion of the surface pattern is attached to a top surface of a terminal pad of the lead. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The die contact area of the clip is attached to a top contact on the semiconductor die. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead.

An integrated circuit package includes a leadframe with a die pad and a lead. A semiconductor die is attached to a top surface of the die pad. A clip has a lead contact area with a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. A portion of the surface pattern is attached to a top surface of a terminal pad of the lead. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The die contact area of the clip is attached to a top contact on the semiconductor die. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead.

An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

Provided is a semiconductor module comprising a semiconductor chip, a lead frame including a chip connection portion configured to connect the lead frame to the semiconductor chip, and a bonding member configured to connect the chip connection portion and the semiconductor chip, wherein the semiconductor chip includes a semiconductor substrate, an active portion provided on the semiconductor substrate, and a transverse protective film provided above the active portion and provided to traverse the active portion in a top view, wherein the chip connection portion includes a center portion which covers a center of the transverse protective film in a top view and a first cut-out portion provided from a first end side of the chip connection portion towards the center portion.

Provided is a semiconductor module comprising a semiconductor chip, a lead frame including a chip connection portion configured to connect the lead frame to the semiconductor chip, and a bonding member configured to connect the chip connection portion and the semiconductor chip, wherein the semiconductor chip includes a semiconductor substrate, an active portion provided on the semiconductor substrate, and a transverse protective film provided above the active portion and provided to traverse the active portion in a top view, wherein the chip connection portion includes a center portion which covers a center of the transverse protective film in a top view and a first cut-out portion provided from a first end side of the chip connection portion towards the center portion.

An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.

An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.