Patent classifications
H01L2224/85186
Semiconductor device
Electrode pads disposed on a first surface of a semiconductor element include a first pad located close to a corner and a second pad located apart from the corner compared with the first pad. A first wire connected to the first pad has a smaller Young's modulus than a second wire connected to the second pad. A thickness of an intermetallic compound layer formed by the first wire and the first pad is larger than a thickness of an intermetallic compound layer formed by the second wire and the second pad.
Semiconductor device
A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.
Semiconductor device
A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.
Bonding pad arrangement design for multi-die semiconductor package structure
A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.
Method of manufacturing semiconductor device and wire bonding apparatus
A method of manufacturing a semiconductor device includes: a wire tail forming step of forming a wire loop 130 between a first bonding point and a second bonding point with a bonding tool 40, and then cutting a portion of a wire 42 extending from a tip of the bonding tool 40 to thereby form a wire tail 43 at the tip of the bonding tool 40; and a wire tail bending step of bending the wire tail 43 so as to direct a tip 43a of the wire tail 43 upward by descending the bonding tool 40 toward the second bonding point with the wire loop 130 formed thereat and pressing the wire tail 43 against a portion of the wire loop 130 located above the second bonding point. Thus, the wire tail can be bent easily and efficiently.
MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME
A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.
MANUFACTURING METHOD OF PACKAGE-ON-PACKAGE STRUCTURE
A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.
MANUFACTURING METHOD OF PACKAGE-ON-PACKAGE STRUCTURE
A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure and a manufacturing method thereof are provided. The package structure includes a circuit carrier, a substrate, a die, a plurality of conductive wires and an encapsulant. The substrate is disposed on the circuit carrier and includes a plurality of openings. The die is disposed between the circuit carrier and the substrate. The conductive wires go through the openings of the substrate to electrically connect between the substrate and the circuit carrier. The encapsulant is disposed on the circuit carrier and encapsulates the die, the substrate and the conductive wires.